DAC5682Z_09 datasheet(21/59 Pages) TI

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DAC5682Z

www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_lock

DLL_lock

Unused

device_ID(2:0)

version(1:0)

PLL_lock:

Asserted when the internal PLL is locked. (Read Only)

DLL_lock:

Asserted when the internal DLL is locked. Once the DLL is locked, this bit should remain a

‘1’ unless the DCLK input clock is removed or abruptly changes frequency causing the DLL

to fall out of lock. (Read Only)

device_ID(2:0):

Returns ‘000’ for DAC5682Z Device_ID code. (ReadOnly)

version(1:0):

A hardwired register that contains the register set version of the chip. (ReadOnly)

version (1:0)

Identification

‘01’

PG1.0 Initial Register Set

‘10’

PG1.1 Register Set

‘11'

Production Register Set

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DAC_delay(1:0)

Unused

FIR_ena

SLFTST_ena

FIFO_offset(2:0)

DAC_delay(1:0):

DAC data delay adjustment. (0–3 periods of the DAC clock) This can be used to adjust

system level output timing. The same delay is applied to both DACA and DACB data paths.

FIR_ena:

When set, the interpolation filters are enabled.

SLFTST_ena:

When set, a Digital Self Test (SLFTST) of the core logic is enabled. Refer to Digital Self

Test Mode section for details on SLFTST operation.

FIFO_offset(2:0):

Programs the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to

+3 positions upon SYNC. Default offset is 0 and is updated upon each sync event – unless

disabled via FIFO_sync_dis in CONFIG5 register.

FIFO_offset(2:0)

Offset

011

010

001

000

111

–1

110

–2

101

–3

100

–4

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