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HD74LV166A Datenblatt(PDF) 6 Page - Renesas Technology Corp

Teilenummer HD74LV166A
Bauteilbeschribung  Parallel-Load 8-bit Shift Register
PDF  10 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD74LV166A Datenblatt(HTML) 6 Page - Renesas Technology Corp

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HD74LV166A
Preliminary
R04DS0002EJ0400 Rev.4.00
Page 6 of 9
Aug 16, 2010
Switching Characteristics
(VCC = 2.5 ± 0.2 V)
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
FROM
(Input)
TO
(Output)
50
80
45
CL = 15 pF
Maximum clock
frequency
fmax
40
65
35
MHz
CL = 50 pF
12.2
19.8
1.0
22.0
CL = 15 pF
tPLH/tPHL
15.3
23.3
1.0
26.0
CL = 50 pF
CLK
10.8
16.0
1.0
18.0
CL = 15 pF
Propagation
delay time
tPHL
14.2
19.5
1.0
22.0
ns
CL = 50 pF
CLR
QH
6.0
7.0
CLR inactive before CLK
7.0
7.0
CLK INH before CLK
6.5
8.5
Data before CLK
7.0
8.5
SH/
LD high before CLK
Setup time
tsu
8.5
9.5
ns
SER before CLK
–0.5
0.0
PAR data after SH/
LD 
–0.5
0.0
SER data after CLK
Hold time
th
–0.5
0.0
ns
SH/LD high after CLK
8.0
9.0
CLR low
Pulse width
tw
8.5
9.0
ns
CLK H or L
(VCC = 3.3 ± 0.3 V)
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
FROM
(Input)
TO
(Output)
65
115
55
CL = 15 pF
Maximum clock
frequency
fmax
60
90
50
MHz
CL = 50 pF
8.6
15.4
1.0
18.0
CL = 15 pF
tPLH/tPHL
10.9
18.9
1.0
21.5
CL = 50 pF
CLK
7.9
12.5
1.0
15.0
CL = 15 pF
Propagation
delay time
tPHL
10.4
16.3
1.0
18.5
ns
CL = 50 pF
CLR
QH
4.0
4.0
CLR inactive before
CLK
5.0
5.0
CLK INH before CLK
5.0
6.0
Data before CLK
5.0
6.0
SH/
LD high before CLK
Setup time
tsu
5.0
6.0
ns
SER before CLK
0.0
0.0
PAR data after SH/
LD 
0.0
0.0
SER data after CLK
Hold time
th
0.0
0.0
ns
SH/LD high after CLK
6.0
7.0
CLR low
Pulse width
tw
6.0
7.0
ns
CLK H or L



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