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PCA2000UAC Datenblatt(PDF) 3 Page - NXP Semiconductors |
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PCA2000UAC Datenblatt(HTML) 3 Page - NXP Semiconductors |
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3 / 30 page ![]() PCA2000_2001 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 23 August 2010 3 of 30 NXP Semiconductors PCA2000; PCA2001 32 kHz watch circuit with programmable adaptive motor pulse 5. Block diagram 6. Pinning information 6.1 Pinning Fig 1. Block diagram of PCA2000 and PCA2001 mgw567 ÷4 MOT2 MOT1 8 3 5 1 2 67 RESET 4 VDD VSS VOLTAGE DETECTOR, OTP-CONTROLLER MOTOR CONTROL WITH ADAPTIVE PULSE MODULATION STEP DETECTION EOL PCA2000 only PCA2000 PCA2001 DIVIDER RESET reset 32 Hz 1 Hz 8 kHz OSCILLATOR OSCIN OSCOUT i.c. OTP-MEMORY TIMING ADJUSTMENT, INHIBITION a. Top view. For mechanical details, see Figure 13. b. Top view. For mechanical details, see Figure 14. Fig 2. Pad and bump configuration of PCA2000 and PCA2001 001aai177 PCA200xU 1 VSS 8 RESET 2 i.c. 7 MOT2 3 OSCIN 6 MOT1 4 OSCOUT 5 VDD x y 0 0 001aai176 PCA200xCX 1 VSS 8 RESET 2 i.c. 7 MOT2 3 OSCIN 6 MOT1 4 OSCOUT 5 VDD x y 0 0 |
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