DP35DP datasheet(67/84 Pages) INTEL

67 / 84 page

Error Messages and Beep Codes

Table 37. Port 80h POST Codes

POST Code

Description of POST Operation

Host Processor

Power-on initialization of the host processor (Boot Strap Processor)

Host processor cache initialization (including APs)

Starting Application processor initialization

SMM initialization

Chipset

Initializing a chipset component

Memory

Reading SPD from memory DIMMs

Detecting presence of memory DIMMs

Programming timing parameters in the memory controller and the DIMMs

Configuring memory

Optimizing memory settings

Initializing memory, such as ECC init

Testing memory

PCI Bus

Enumerating PCI busses

Allocating resources to PCI bus

Hot Plug PCI controller initialization

53 – 57

Reserved for PCI Bus

USB

Resetting USB bus

Reserved for USB

ATA/ATAPI/SATA

Resetting PATA/SATA bus and all devices

Reserved for ATA

SMBus

Resetting SMBus

Reserved for SMBus

Local Console

Resetting the VGA controller

Disabling the VGA controller

Enabling the VGA controller

Remote Console

Resetting the console controller

Disabling the console controller

Enabling the console controller

continued

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