MPC8568E datasheet(16/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Input Clocks

4.2

PCI Clock Timing

Table 8 provides the PCI clock (PCI_CLK) AC timing specifications for the MPC8568E.

4.3

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the Time Base unit of the e500. There is no need for jitter

specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2

× tCCB, and minimum clock low time is 2 × tCCB. There is

no minimum RTC frequency. RTC may be grounded if not needed.

SYSCLK jitter

—

+/– 150

4, 5

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective

maximum or minimum operating frequencies. Refer to Section 23.2, “CCB/SYSCLK PLL Ratio and Section 23.3,

“e500 Core PLL Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

Table 8. PCI_CLK AC Timing Specifications

At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

PCI_CLK frequency

fPCI_CLK

——

66.7

MHz

—

PCI_CLK cycle time

tPCI_CLK

—

PCI_CLK rise and fall time

tKH, tKL

0.6

1.0

2.3

PCI_CLK duty cycle

tKHK/tPCI_CLK

—

PCI_CLK jitter

—

+/– 150

3,4

Notes:

1. Rise and fall times for PCI_CLK are measured at 0.4 V and 2.7 V.

2. Timing is guaranteed by design and characterization.

3. This represents the total input jitter—short term and long term—and is guaranteed by design.

4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

Table 7. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

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