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LC72P366 Datenblatt(PDF) 5 Page - Sanyo Semicon Device

Teilenummer LC72P366
Bauteilbeschribung  On-Chip One-Time Programmable PROM Single-Chip PLL Controller
PDF  14 Pages
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Hersteller  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC72P366 Datenblatt(HTML) 5 Page - Sanyo Semicon Device

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No. 5544-5/14
LC72P366
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
IIH(1)
XIN : VI = VDD = 5.0 V
2.0
5.0
15
µA
IIH(2)
FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0 V
4.0
10
30
µA
Ports A, E, F, G, H, I, K, L, M, and Q,
SNS, HOLD, HCTR, LCTR, and with no
Input high-level current
IIH(3)
pull-down resistor on port A, VI = VDD = 5.0 V
3.0
µA
With input mode selected for ports
E, F, G, K, L, M, and Q
IIH(4)
Port A: pull-down resistor present
50
µA
IIL(1)
XIN:VI = VSS
2.0
5.0
15
µA
IIL(2)
FMIN, AMIN, HCTR, LCTR : VSS
4.0
10
30
µA
Ports A, E, F, G, H, I, K, L, M, and Q,
Input low-level current
SNS, HOLD, HCTR, LCTR, and with no
IIL(3)
pull-down resistor on port A, VI = VSS
3.0
µA
With input mode selected for ports E, F,
G, K, L, M, and Q
Input floating voltage
VIF
Port A: pull-down resistor present
0.05 VDD
V
Pull-down resistance
RPD(1)
Port A: pull-down resistor present VDD = 5 V
75
100
200
k
RPD(2)
TEST1, TEST2
10
k
Hysteresis
VH
Ports F, G, and K, LCTR (in period measurement mode)
0.1 VDD
0.2 VDD
V
VOH(1)
Ports B and C: IO = –1 mA
VDD – 2.0
VDD – 1.0
V
Output high-level voltage
VOH(2)
Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = –1 mA
VDD – 1.0
V
VOH(3)
EO1, EO2, EO3, SUBPD : IO = –500 µA
VDD – 1.0
V
VOH(4)
XOUT : IO = –200 µA
VDD – 1.0
V
VOL(1)
Ports B and C: IO = 50 µA
1.0
2.0
V
VOL(2)
Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = 1 mA
1.0
V
Output low-level voltage
VOL(3)
EO1, EO2, EO3, SUBPD : IO = 500 µA
1.0
VOL(4)
XOUT : IO = 200 µA
1.5
VOL(5)
Port J: IO = 5 mA
2.0
V
IOFF(1)
Ports B, C, D, E, F, G, K, L, M, N, O, P, and Q
–3.0
+3.0
µA
Output off leakage current
IOFF(2)
EO1, EO2, EO3, SUBPD
–100
+100
nA
IOFF(3)
Port J
–5.0
+5.0
µA
A/D conversion error
ADI0 to ADI5 : VDD(1)
–1/2
+1/2
LSB
Rejected pulse width
PREJ
SNS
50
µs
Power down detection voltage
VDET
3.0
3.5
4.0
V
IDD(1)
VDD(1) : fIN(2) = 130 MHz, Ta = 25˚C
12
24
mA
IDD(2)
VDD(2): halt mode*, Ta = 25˚C (See figure 1.)
0.45
mA
Current drain
IDD(3)
VDD = 5.5 V, oscillator stopped
5
µA
Ta = 25˚C (See figure 2.)
IDD(4)
VDD = 2.5 V, oscillator stopped
1
µA
Ta = 25°C (See figure 2.)
Electrical Characteristics in the Allowable Operating Ranges
Note: * Executing 20 STEP instructions every millisecond. With the PLL and counter circuits stopped.
Note: With PB to PG, and PJ to PQ all open.
However, with PE to PG, PK to PM, and PQ selected for output.
Figure 1 IDD(2) in Halt Mode
Note: With PA to PQ all open.
Figure 2 IDD(3) and IDD(4) in Backup Mode
Test Circuit Diagrams



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