Waveforms for the Microprocessor Interface Block

Input mode

Output mode

Clock Modes

The LC8901 and LC8901Q support 4 clock modes selected by the XSYS and CLK pins.

1. When the CLK pin is low, the 256fs clock duty is H:L = 2:1.

2. When the CLK pin is high, the duty is 1:1.

3. Modes in which XSYS is high assume the analog source mode from the usage overview diagram.

4. The LSI automatically switches to analog source mode if there is no signal applied to the data demodulation input

pin.

5. The STOP pin controls stopping the VCO. In analog source mode, the system will not stop if the STOP pin is set

high. However, setting this pin high in digital source mode while the PLL circuit is operating will stop the system.

No. 4079-8/15

LC8901, 8901Q

XSYS pin

CLK pin

Mode

L

L

The system clock is 384fs. It is synchronized to the input data, which is then demodulated.

L

H

The system clock is 512fs. It is synchronized to the input data, which is then demodulated.

H

L

The system clock is 384fs, but data is neither synchronized nor demodulated. The 256fs, BCLK, and LRCK signals are

output based on the crystal oscillator.

H

H

The system clock is 512fs, but data is neither synchronized nor demodulated. The 256fs, BCLK, and LRCK signals are

output based on the crystal oscillator.