PIC24FV32KA304 datasheet(56/320 Pages) MICROCHIP

56 / 320 page

 2011 Microchip Technology Inc.

DS39995B-page 56

PIC24FV32KA304 FAMILY

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”

For all table operations, the area of program memory

space to be accessed is determined by the Table

Memory Page Address register (TBLPAG). TBLPAG

covers the entire program memory space of the

device, including user and configuration spaces. When

TBLPAG<7> = 0, the table page is located in the user

memory space. When TBLPAG<7> = 1, the page is

located in configuration space.

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Note:

Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas, such as the

Device ID. Table write operations are not

allowed.

00000000

‘Phantom’ Byte

TBLRDH.B

(Wn<0> = 0)

TBLRDL.W

TBLRDL.B

(Wn<0> = 1)

TBLRDL.B

(Wn<0> = 0)

TBLPAG

000000h

800000h

002BFEh

Program Space

Data EA<15:0>

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register. Only read

operations are provided; write operations are also valid in the

user memory area.

PIC24FV32KA304 Datenblatt(PDF) 56 Page - Microchip Technology

PIC24FV32KA304 Datenblatt(HTML) 56 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL