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PD67124AM Datenblatt(PDF) 11 Page - Microsemi Corporation |
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PD67124AM Datenblatt(HTML) 11 Page - Microsemi Corporation |
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11 / 14 page ![]() PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM Data Sheet (Non-confidential) Copyright © 2009 Microsemi Page 10 Rev. 1.0 / 17-March-10 Analog Mixed Signal Group 2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 Enhanced Mode PD671xxx DIMM Block Diagram Figure 8 illustrates the internal circuitry of the Enhanced Mode DIMM Master. PD69012 appears only in one of the 12 port circuits. Figure 8: PD67124M DIMM, Internal Block Diagram Top Assembly Description The following sections detail the top assembly components. Power Supply The entire circuit is powered by a nominal 48 VDC potential (Vmain can range from 44 to 57 VDC for AF mode and 50 to 57 VDC for AT high power mode). 3.3 VDC Regulator Each of the PD69012 includes a 3.3 VDC regulator (EXT_REG and 3_3Vout) for up to 6 mA. This current is utilized for powering external components in the PoE domain. There is an option of adding a driver to this output to drive higher loads. Q1 provides up to 30 mA to the PoE controller and to the opto-couplers in the interface circuit. The total capacitance on the 3.3 VDC should be less then 4.7 uF (with and without an external driver). Grounds The overall circuit includes two physical ground planes, analog and digital, which are electrically connected at a single point on the motherboard (see Figure 9 and Figure 10). This method, used throughout the design, improves noise immunity and coupling. Application note AN-132, Catalogue Number 06-0010-080 provides further details about this design technique. Control Signals Several control signals are utilized between the switch and the PoE circuitry: xReset_In: Driven by the switch circuitry to reset the PoE circuit. xDISABLE_PORTS : Driven by the switch, to disable all PoE ports immediately. Indication Signals Int_out: Enables the Host CPU to reduce the communication volume whenever a PoE event masked by the Host CPU occurs. The PoE Controller sends an interrupt for indication. System_ok: (Enhanced mode only) An optional hardware single line, driven by the Master DIMM to the Host CPU; this signal provides the Host CPU with a warning that a major failure such as Vmain out of range has occurred. |
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