 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
FULLFLEX Datenblatt(PDF) 26 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
FULLFLEX Datenblatt(HTML) 26 Page - Cypress Semiconductor |
|
|
26 / 52 page  FullFlex Document Number: 38-06082 Rev. *K Page 26 of 52 Switching Characteristics Over the Operating Range Table 13. SDR Mode, Signals Affected by DLL Parameter Description DLL ON (LOWSPD=1)[46] DLL OFF (LOWSPD=0)[46] -200 -167 Unit Min Max Min Max Min Max tCD2[49] C rise to DQ valid for pipelined mode –3.30[45, 48] –4.00[45, 48] –6.00[45, 48] ns tCCQ[49] C rise to CQ rise 1.00 3.30 [48] 1.00 4.00[48] 1.00 6.00[48] ns tCKHZ2[44, 49] C rise to DQ output high Z in pipelined mode 1.00 3.30[45, 48] 1.00 4.00[45, 48] 1.00 6.00[45, 48] ns tCKLZ2[44, 49] C rise to DQ output low Z in pipelined mode 1.00 – 1.00 – 1.00 – ns Table 14. SDR Mode Parameter Description -200 -167 Unit Min Max Min Max fMAX (PIPELINED) Maximum operating frequency for pipelined mode 100 200 100 167 MHz fMAX (FLOW THROUGH ) Maximum operating frequency for flow through mode – 77 – 66.7 MHz tCYC (PIPELINED) C clock cycle time for pipelined mode 5.00[48] 10.00 6.00[48] 10.00 ns tCYC (FLOW X THROUGH ) C clock cycle time for flow through mode 13.00[48] –15.00[48] –ns tCKD C clock duty time 45 55 45 55 % tSD Data input setup time to C rise HSTL 1.8 V LVCMOS 1.50[45, 48] –1.70[45, 48] –ns 2.5 V LVCMOS 3.3 V LVTTL 1.75[45, 48] –1.95[45, 48] ns tHD[47] Data input hold time after C rise 0.5 – 0.5 – ns tSAC Address and control input setup time to C rise HSTL 1.8 V L VCMOS 1.50[45, 47, 48] –1.70[45, 47, 48] –ns 2.5 V LVCMOS 3.3 V LVTTL 1.75[45, 47, 48] –1.95[45, 47, 48] –ns tHAC[47] Address and control input hold time after C rise 0.50 – 0.60 – ns tOE Output enable to data valid – 4.40[45, 48] –5.00[45, 48] ns tOLZ[44] OE to low Z 1.00 – 1.00 – ns Notes 44. Parameters specified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25. 45. For the x18 devices, add 200 ps to this parameter in Table 14. 46. Test conditions assume a signal transition time of 2 V/ns. 47. Add 300 ps to this timing for 36M devices. 48. Add 15% to this parameter if a VCORE of 1.5 V is used. 49. This parameter assumes input clock cycle to cycle jitter of ± 0ps. [+] Feedback |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
