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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PIC24F08KA102 Datenblatt(PDF) 3 Page - Microchip Technology |
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PIC24F08KA102 Datenblatt(HTML) 3 Page - Microchip Technology |
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3 / 48 page  PIC24FXXKAXXX © 2008 Microchip Technology Inc. Advance Information DS39919A-page 3 TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING) 2.4 Memory Map The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map, and supports up to 5.5K instruction words (about 16 Kbytes). Table 2-3 provides the program memory size and number of program memory rows present in each device variant. The PIC24FXXKA1XX family devices have an on-chip data EEPROM. This data EEPROM is mapped to the program memory area from location 7FFE00h to 7FFFFEh. Table 2-4 provides the data EEPROM size and the number of rows present in each device variant. The erase operation can be done on one word, half of a row or one row at a time. The program operation can be done only one word at a time. Locations, 800000h through 8007FEh, are reserved for executive code memory. This region stores the programming executive, the debugging executive and the Diagnostic Words. The programming executive is used for device programming, and the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code. The device Configuration registers are implemented from location F80000h to F80010h, and can be erased or programmed one register at a time. Table 2-2 provides the implemented Configuration registers and their locations. Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify the device type that is being programmed. See Section 6.0 “Device ID” for more information. The Device ID registers read out normally even after code protection is applied. Figure 2-3 depicts the memory map for the PIC24FXXKAXXX family variants. TABLE 2-2: CONFIGURATION REGISTER LOCATIONS TABLE 2-3: CODE MEMORY SIZE TABLE 2-4: DATA EEPROM MEMORY SIZE Pin Name During Programming Pin Name Pin Type Pin Description MCLR/VPP MCLR/VPP P Programming Enable VDD VDD P Power Supply VSS VSS PGround PGCx PGC I Programming Pin Pair: Serial Clock PGDx PGD I/O Programming Pin Pair: Serial Data Legend: I = Input, O = Output, P = Power Configuration Register Address FBS F80000 FGS F80004 FOSCSEL F80006 FOSC F80008 FWDT F8000A FPOR F8000C FICD F8000E FDS F80010 PIC24FXXKAXXX Device User Memory No. of Address Limit (Instruction Words) No. of Rows PIC24F08KA101 15FE (2.75K) 88 PIC24F16KA101 2BFE (5.5K) 176 PIC24F08KA102 15FE (2.75K) 88 PIC24F16KA102 2BFE (5.5K) 176 PIC24F04KA200 AFE (1.375K) 44 PIC24F04KA201 AFE (1.375K) 44 Note: An erase operation can be performed on one, two or four rows at a time, and a program operation can be performed on one row at a time. PIC24FXXKA1XX Device Data EEPROM Size in Words No. of Rows PIC24F08KA101 256 32 PIC24F16KA101 256 32 PIC24F08KA102 256 32 PIC24F16KA102 256 32 Note: An erase operation can be performed on one, four or eight words at a time and a program operation can be performed on one word at a time. |
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