L6738 datasheet(22/32 Pages) STMICROELECTRONICS

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Application details

L6738

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Doc ID 18133 Rev 1

Application details

9.1

Compensation network

The control loop shown in

Figure 9 is a voltage mode control loop. The output voltage is

regulated to the internal reference (when present, an offset resistor between FB node and

GND can be neglected in control loop calculation).

Error amplifier output is compared to the oscillator sawtooth waveform to provide a PWM

signal to the driver section. The PWM signal is then transferred to the switching node with

VIN amplitude. This waveform is filtered by the output filter.

The converter transfer function is the small signal transfer function between the output of the

EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT

resonance and a zero at FESR depending on the output capacitor ESR. The DC gain of the

modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage

∆VOSC.

Figure 9.

PWM control loop

The compensation network closes the loop joining VOUT and EA output with transfer

function ideally equal to -Z

F/ZFB.

Compensation goal is to close to the control loop assuring high DC regulation accuracy,

good dynamic performance and stability. To achieve this, the overall loop needs high DC

gain, high bandwidth and good phase margin.

High DC gain is achieved giving an integrator shape to compensation network transfer

function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for

stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain

has to cross the 0dB axis with -20dB/decade slope.

For example,

Figure 10 shows an asymptotic bode plot of a type III compensation.

OUT

ESR

OSC

∆V

OSC

OUT

REF

PWM

COMPARATOR

ERROR

AMPLIFIER

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