TMP320LC2401AVFS datasheet(48/88 Pages) TI

48 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

digital I/O and shared pin functions

The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared

between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O

ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and

shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:

D Output Control Registers — used to control the multiplexer selection that chooses between the primary

function of a pin or the general-purpose I/O function.

D Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.

description of shared I/O pins

Each shared I/O pin has three bits that define its operation:

D MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.

D I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines

whether the pin is an input (0) or an output (1).

D I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected

is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.

The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.

A summary of shared pin configurations and associated bits is shown in Table 10.

Table 10. Shared Pin Configurations

PIN FUNCTION SELECTED

MUX

MUX CONTROL

I/O PORT DATA AND DIRECTION†

(MCRA.n = 1)

Primary Function

(MCRA.n = 0)

Secondary

Function

MUX

CONTROL

(name.bit #)

MUX CONTROL

VALUE AT

RESET

(MCRx.n)

DATA BIT NO.‡

DIR BIT NO.§

PORT A

PDPINTA

IOPA0¶

MCRA.0

PADATDIR

PWM1

IOPA1

MCRA.1

PADATDIR

PWM2

IOPA2

MCRA.2

PADATDIR

PWM3

IOPA3

MCRA.3

PADATDIR

PWM4

IOPA4

MCRA.4

PADATDIR

PWM5

IOPA5

MCRA.5

PADATDIR

PWM6

IOPA6

MCRA.6

PADATDIR

CLKOUT

XINT2/ADCSOC/

CAP1/IOPA7

MCRA.7

PADATDIR

PORT B

T2PWM

XINT1/IOPB0

MCRA.8

PBDATDIR

IOPB1

MCRA.9

PBDATDIR

IOPB2

MCRA.10

PBDATDIR

SCITXD

IOPB3

MCRA.11

PBDATDIR

SCIRXD

IOPB4

MCRA.12

PBDATDIR

OPB5

MCRA.13

PBDATDIR

−

MCRA.14

PBDATDIR

−

MCRA.15

PBDATDIR

† Valid only if the I/O function is selected on the pin

‡ If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.

§ If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.

¶ Even when MCRA.0 = 0, the PDPINT circuitry is still active.

TMP320LC2401AVFS Datenblatt(PDF) 48 Page - Texas Instruments

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