LH521028 datasheet(13/15 Pages) SHARP

13 / 15 page

BYTE OPERATIONS

Byte Read Description (Figure 12)

To read individual bytes, the device must be enabled

(E is LOW), W must be HIGH, the outputs must be

enabled (G is LOW) and the addresses must be either

stable or latched with ALE. Figure 12 is one example of

the byte read capabilities of this device. The example

shows two read operations. The first is a read of the high

byte of the current memory location and the second is a

read of the low byte of the memory location.

(1) At the beginning of the cycle both SL and SH are

HIGH.

(2) SH goes LOW initiating a Read on the upper byte

DQH(9-17). SL remains HIGH keeping the lower byte

DQL(0-8) disabled and in a high-impedance mode.

(3) SL goes LOW activating DQL(0-8).Valid data is avail-

able in tSA following SL going LOW.

(4) When SH goes HIGH, DQH(9-17) remains valid for tSHZ

before returning to a high-impedance condition.

(5) Finally, the Read for the lower byte is terminated by

deasserting SL (HIGH). DQL(0-8) remains active for

tSHZ following SL going HIGH.

ADDRESS

VALID DATA

ALE

DQL (0-8)

DQH (9-17)

(1) (2)

(3)

(4)

(5)

521028-10

VALID ADDRESS

Figure 12.

Byte Read (E is LOW and W is HIGH)

CMOS 64K

× 18 Static RAM

LH521028

4-223

LH521028 Datenblatt(PDF) 13 Page - Sharp Corporation