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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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LH521028A Datenblatt(PDF) 1 Page - Sharp Corporation |
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LH521028A Datenblatt(HTML) 1 Page - Sharp Corporation |
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1 / 15 page  LH521028A CMOS 64K × 18 Static RAM FEATURES •• Fast Access Times: 15/17/20/25/35 ns •• Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity •• Transparent Address Latch •• Reduced Loading on Address Bus •• Low-Power Stand-by Mode when Deselected •• TTL Compatible I/O •• 5 V ± 10% Supply •• 2 V Data Retention •• JEDEC Standard Pinout •• Package: 52-Pin PLCC FUNCTIONAL DESCRIPTION The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix con- structed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation. The control signals include Write Enable (W), Chip Enable (E), High and Low Byte Select (SL and SH), Output Enable (G) and Address Latch Enable (ALE). The wide word provides for reduced component count, improved density, reduced Address bus loading and improved per- formance. The wide word also allows for byte-parity with no additional RAM required. This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH).The Byte-select controls, SH and SL, are also used to enable or disable Read and Write operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applica- tions not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address bus buffers and/or latches. Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is trans- ferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control (G) can prevent bus contention. When E and either SH or SL are LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address with ALE HIGH. PIN CONNECTIONS 521028-1D 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 7 6 5 4 3 2 1 5251 504948 47 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 52-PIN PLCC TOP VIEW Figure 1. Pin Connections for PLCC Package 1 |
Ähnliche Teilenummer - LH521028A |
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Ähnliche Beschreibung - LH521028A |
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