ZL2103 datasheet(17/28 Pages) INTERSIL

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ZL2103

FN6966.5

May 3, 2011

In the event of a loss of the external clock signal, the output

voltage may show transient over/undershoot. If this happens, the

ZL2103 will automatically switch to its internal oscillator and

switch at a frequency close to the previous incoming frequency.

CONFIGURATION C: SYNC AUTO DETECT

When the SYNC pin is configured in auto detect mode (CFG pin is

left OPEN), the device will automatically check for a clock signal

on the SYNC pin after enable is asserted. If a valid clock signal is

present, the ZL2103’s oscillator will then synchronize with the

rising edge of the external clock (refer to SYNC INPUT

description).

If no incoming clock signal is present, the ZL2103 will configure

the switching frequency according to the state of the SYNC pin as

listed in Table 8. In this mode, the ZL2103 will only read the

SYNC pin connection during the start-up sequence. Changes to

the SYNC pin connection will not affect fSW until the power

(VDDS) is cycled off and on again.

If the user wishes to run the ZL2103 at a frequency not listed in

Table 8, the switching frequency can be set using an external

resistor, RSYNC, connected between SYNC and SGND using

Table 9.

The switching frequency can also be set to any value between

200kHz and 1MHz using the I2C/SMBus interface. The available

frequencies are defined by

fSW = 8MHz/N, where whole number N is 8 ≤ N ≤ 40. See

Application Note AN2033 for details.

If a value other than fSW = 8MHz/N is entered using a PMBus

command, the internal circuitry will select the valid switching

frequency value that is closest to the entered value. For example,

if 810kHz is entered, the device will select 800kHz (N=10).

Note: The switching frequency read back using the appropriate

PMBus command will differ slightly from the selected value in

Table 9. The difference is due to hardware quantization.

When multiple Zilker Labs devices are used together, connecting

the SYNC pins together will force all devices to synchronize with

each other. The CFG pin of one device must set its SYNC pin as an

output and the remaining devices must have their SYNC pins set

as an input or as auto detect.

Note: Precise ramp timing mode must be disabled to use SYNC

clock auto detect.

Component Selection

The ZL2103 is a synchronous buck converter with integrated

MOSFETs that uses an external inductor and capacitors to

perform the power conversion process. The proper selection of

the external components is critical for optimized performance.

To select the appropriate external components for the desired

performance goals, the power supply requirements listed in

Table 10 must be defined.

DESIGN GOAL TRADE-OFFS

The design of the buck power stage requires several

compromises among size, efficiency and cost. The inductor core

loss increases with frequency, so there is a trade-off between a

TABLE 8. SWITCHING FREQUENCY SELECTION

SYNC PIN

FREQUENCY

LOW

200kHz

OPEN

400kHz

HIGH

1MHz

Resistor

See Table

TABLE 9. RSYNC RESISTOR VALUES

RSYNC

Ω)

FSW

(kHz)

200

222

12.1

242

13.3

267

14.7

296

16.2

320

17.8

364

19.6

400

21.5

421

23.7

471

26.1

533

28.7

571

31.6

615

34.8

667

38.3

727

42.2

889

46.4

1000

TABLE 10. POWER SUPPLY REQUIREMENTS

PARAMETER

RANGE

EXAMPLE

VALUE

Input voltage (VIN)4.5V to

14.0V

12V

Output voltage (VOUT)0.6V to

5.0V

3.3V

Output current (IOUT)

0A to 3A

Output voltage ripple (Vorip)

< 3% of

VOUT

±1% of VOUT

Output load step (Iostep)< Io

±25% of Io

Output load step rate

2.5A/µs

Output deviation due to load step

±3% of VOUT

Maximum PCB temp.

+120°C

+85°C

Desired efficiency

85%

Other considerations

Optimize for small

size

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