ICS1532 datasheet(13/36 Pages) IDT

13 / 36 page

110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

MDS 1532 G

Revision 060804

www.idt.com

ICS1532

05h

DPA Control

R/W. D-DPA.

7-2 Reserved

Reserved

–

1-0 DPA_Res

DPA resolution (Number of available Delay Elements)

See Chapter 5, “DPA Operation”

– 00 = 16 elements - supports 55 to 110 MHz

– 01 = 32 elements - supports 27 to 110 MHz

– 10 = Reserved

– 11 = 64 elements - supports 14 to 64 MHz

N/A

06h

Output Enables R/W

Reserved

OE_TCLK

Enable CLK output to ADC and CLK pin

1 = MUST be Enabled for Normal Operation

OE_ADCRCLK

Enable ADCRCLK clock output

OE_ADCSYNC

Enable output for ADCSYNC

FUNC_Sel

Select signal source for ADC_FUNC signal

0 = Output of the Feedback Divider - Normal Operation

1 = ADC_FUNC output is REF

FUNC_Delay

Additional one CLK delay for ADC_FUNC signal

Reserved

07h

OSC Divider

R/W

7-0 OSC_Div

Oscillator divider value

– 00000000 = Reserved.

– 00000001 = (OSC / 2)

– 00000010 = (OSC / 2) / 2

– 00000011 = (OSC / 2) / 3, and so forth.

08h

Internal Filter

R/W

Shunt_Sel

Select additional Cp capacitor

Values?

6-4 Res_Sel

Select additional Rs resistance

Values?

3-1 Cap_Sel

Select additional Cs capacitance

Fil_Sel

Selects Loop Filter Select

1 = Internal (Typical)

0=External

09h

Reserved

N/A

0Ah

Pixel PLL/

DPA Resets

Write

7-4 Pixel PLL Reset

Writing 5xh resets pixel PLL and loads working Regs

1h through 3h

N/A

3-0 DPA Reset

Writing xAh resets DPA and loads working Reg 5h

N/A

0Bh-0Fh Reserved

N/A

10h

Chip Ver

Read

7-0 Chip Ver

Read chip version 32 decimal (20h) as in 1532

11h

Chip Rev

Read. IN-A.

7-4 Chip Major Rev

Value increments with major chip revision.

Table 4-2.

New Register Set Outline (Continued)

Index

Access

Bit #

Bit Name

Brief Description

Reset

Value

OSC Period

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