TUSB8040RKMR datasheet(20/33 Pages) TI

20 / 33 page

TUSB8040

SLLSE42F

– SEPTEMBER 2010 – REVISED OCTOBER 2011

www.ti.com

Table 3-13. Bit Descriptions

– Device Configuration Register (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

U1 U2 Disable

When this bit is set, the TUSB8040 will not initiate or accept any U1 or U2 requests on any

port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP

command. After receiving or sending a FLPMA LMP command, the TUSB8040 will

continue to enable U1 or U2 until it gets a power on reset or is disconnected on its

u1u2Disable

upstream port.

This bit is loaded at the deassertion of reset with the value of the SDA_SMDAT terminal.

When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the

EEPROM.

When the TUSB8040 is in SMBUS mode, the value may be over-written by a SMBUS host.

Port Indicator Status.

For the TUSB8040PFP: This bit shall be 1. It shall not be over-written by EEPROM or an

SMBus host.

For the TUSB8040RKM: This bit shall be loaded at the de-assertion of reset with the value

portIndz

of PORTINDz_SMBA3 terminal.

When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the

EEPROM.

When the TUSB8040 is in SMBUS mode, the value may be overwritten by an SMBus host.

Ganged. This bit is always 1.

For the TUSB8040PFP: This bit shall be 1. It shall not be over-written by EEPROM or an

SMBus host.

For the TUSB8040RKM: This bit shall be loaded at the de-assertion of reset with the value

ganged

of GANGEd_SMBA2 terminal.

When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the

EEPROM.

When the TUSB8040 is in SMBUS mode, the value may be overwritten by an SMBus host.

Full Power Management. This bit is loaded at the de-assertion of reset with the value of the

FULLPWRMGMTz_SMBA1 terminal.

fullPwrMgmtz

When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the

EEPROM.

When the TUSB8040 is in SMBUS mode, the value may be over-written by an SMBus host.

1:0

RSVD

Reserved. This field is reserved and returns 0 when read.

3.3.7

Battery Charging Support Register

Table 3-14. Register Offset 6h

BIT NO.

RESET STATE

Table 3-15. Bit Descriptions

– Battery Charging Support Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

RSVD

Reserved. Read only, returns 0 when read.

Battery Charger Support. The bits in this field indicate whether the downstream port

implements the charging port features. A value of 0 indicates the port does not implement

the charging port features. A value of 1 indicates the port does support the charging port

features.

Each bit corresponds directly to a downstream port, i.e. batEn0 corresponds to downstream

port 0.

When in I2C/SMBus mode the bits in this field corresponding to the enabled ports per

used[3:0] may be over-written by EEPROM contents or by an SMBus host.

For the TUSB8040PFP:

3:0

batEn[3:0]

The default value for these bits are loaded at the de-assertion of reset with the value of the

PWRON0z_BATEN0:

Four-port hub - bateEn[3:0] defaults to wxyzb,

where w, x, y and z are all the value of PWRON0z_BATEN0.

For the TUSB8040RKM:

The default value for these bits are loaded at the de-assertion of reset with the value of

PWRON[3:0]z_BATEN[3:0]:

Four-port hub - bateEn[3:0] defaults to wxyzb,

where w is PWRON3z_BATEN3, x is PWRON2z_BATEN2, y is PWRON1z_BATEN1 and z

is PWRON0z_BATEN0.

FUNCTIONAL DESCRIPTION

Submit Documentation Feedback

Product Folder Link(s): TUSB8040

TUSB8040RKMR Datenblatt(PDF) 20 Page - Texas Instruments

TUSB8040RKMR Datenblatt(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datenblatt Download

Link URL