LCS700-708 datasheet(12/26 Pages) POWERINT

12 / 26 page

Rev. B 062011

LCS700-708

www.powerint.com

Resonant Frequency

The series resonant frequency is a function of L

RES and CRES, the

resonant capacitor. For any given value of L

RES, the value of

RES can be adjusted for the desired series resonant frequency

RES. For best efficiency the resonant frequency is set close to

the target operating frequency at nominal input voltage.

Operating Frequency and Frequency Ratio

The operating to resonant frequency ratio f

RATIO is defined as:

RATIO

RES

RATIO = 1 signifies the converter is operating at the series

resonant frequency.

The main determinant of f

RATIO is the transformer turns ratio.

Increasing primary turns lowers f

RATIO for a given input and

output voltage.

The recommended f

RATIO at nominal input voltage is 0.92 – 0.97.

Operating at resonance often yields the highest efficiency for

the resonant powertrain if output rectifier selection is ignored.

However, operating slightly below resonance (which puts the

rectifiers in discontinuous conduction mode), allows the use of

lower voltage diodes or synchronous MOSFETs, which have

lower losses, increasing overall efficiency. This is because at

high-line, when the converter needs to operate above resonance,

the rectifiers operate less deeply in continuous mode, reducing

the magnitude of their current commutation, reducing their stray

inductance voltage spikes. (The stray inductance is comprised

of the leakage inductance between secondary phases and the

stray inductance in the connections to the rectifiers and output

capacitors).

Conversely, operating at a very low f

RATIO (<0.8) results in higher

RMS and peak currents. In some cases, this may result in an

optimal design because it allows the use of lower voltage rating,

lower V

F rectifier as they do not operate in continuous conduction

mode even at high-line, results in no voltage spikes enabling a

lower voltage rating.

An LLC half-bridge converter will operate at resonance when

this equation is true:

OUT

Where n

EQ is the transformer equivalent circuit turns ratio. Note

that the n

EQ of an integrated transformer is lower than its

physical turns ratio N

PRI / NSEC. The secondary turns is that of

each half-secondary. V

OUT in the above equation is equal to

output voltage + diode drop. The divisor “2” is due to the

half-bridge configuration – each half-cycle conducts half the

input voltage to each secondary half.

Note that if the resonant capacitor or inductance value is

changed, both switching frequency and resonant frequency

change, but f

RATIO changes little.

For a given design, the input voltage at which the LLC operates

at resonance is V

INPUT(RESONANCE). Below this voltage, the LLC

operates at a lower frequency (below resonance). Thus for the

recommended f

RATIO ≈ 0.95 at nominal input voltage, VINPUT(RESONANCE)

will be slightly higher than the nominal voltage.

For a design with a variable nominal input voltage (e.g. no PFC

pre-regulator), it is recommended that the initial turns ratio be set

so that V

INPUT(RESONANCE) is at about halfway between maximum and

minimum input voltage. For a design with a variable output voltage

(e.g. constant current regulated output), it is recommended that

the initial turns ratio be set to operate the LLC at resonance at a

point halfway between minimum and maximum output voltages.

Dead-Time Selection

The vast majority of designs using HiperLCS, regardless of power

and operating frequency, work very well with a dead-time of

between 290 and 360 ns. Designs that require a low V

BROWNOUT

tend to require shorter dead-times.

The dead-time setting is a compromise between low-line / full

load (low frequency), and minimum-load / high-line (high-

frequency) conditions. Low-line / full load operation has short

optimal dead-times, while minimum load / high-line has long

optimal dead-times.

A dead-time setting that is longer than optimal for low-line / full

load operation, exhibiting partial loss of ZVS, is acceptable if the

condition does not occur during steady-state operation – i.e.

appears only during transient conditions, such as hold-up time.

Operation with loss of ZVS during steady-state operation leads

to high internal power dissipation and should be avoided.

A dead-time setting that is shorter than optimal for high-line /

minimum-load operation, will tend to cause the feedback sign

to invert and force the HiperLCS to enter burst mode. This is

acceptable if the resulting burst mode operation is acceptable

(i.e. repetition rate does not produce audible noise and if the

large signal transients, wherein the HiperLCS enters and exits

burst mode, is acceptable). Note that with a PFC pre-regulated

front end, a load dump (e.g. 100% to 1% load step) will exhibit a

transient input voltage condition only temporarily (e.g. Input

voltage to LLC stage will increase from 380 V to 410 V and

relatively slowly return to 380 V). Note also that the Burst

Threshold frequency setting is another variable available to the

designer to tune burst mode.

OV/UV Pin

The HiperLCS OV/UV pin which monitors the input (B+) voltage,

has a brown-out shutdown threshold (V

SD(L)) of nominally 79% of

the brown-in (turn-on) threshold (V

SD(H)), which in turn, is nominally

2.4 V. The overvoltage (OV) lockout shutdown threshold (V

OV(H))

is nominally 131% of the brown-in start-up threshold, and the

OV restart point (V

OV(L)) at nominally 126%. The ratios of these

thresholds are fixed and selected for maximum utility in a design

with a PFC pre-regulator front-end with a fixed output voltage

set-point. The resistor divider ratio has to be selected so that

brown-in point is always below the PFC output set-point, and

so that the OV restart (lower) threshold, is always above it,

including component tolerances.

During hold-up time, the voltage will drop from the nominal

value, down to the brown-out threshold, whereby the HiperLCS

will stop switching.

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