LC87F76C8A

No.A0858-21/24

Characteristics of a Sample Main System Clock Oscillation Circuit

Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a

SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values

with which the oscillator vendor confirmed normal and stable oscillation.

Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator

Circuit Constant

Oscillation

Stabilization Time

Nominal

Frequency

Vendor

Name

Oscillator Name

C1

[pF]

C2

[pF]

Rf1

[

Ω]

Rd1

[

Ω]

Operating

Voltage

Range

[V]

typ

[ms]

max

[ms]

Remarks

12MHz

MURATA

CSTCE12M0G52-R0

(10)

(10)

Open

2.2k

2.8 to 5.5

Built-in

C1, C2

CSTCE8M00G52-R0

(10)

(10)

Open

1.0k

8MHz

MURATA

CSTLS8M00G52-R0

(15)

(15)

Open

1.0k

2.5 to 5.5

Built-in

C1, C2

CSTCR4M00F53-R0

(15)

(15)

Open

2.2k

4MHz

MURATA

CSTLS4M0053-B0

(15)

(15)

Open

2.2k

2.1 to 5.5

Built-in

C1, C2

The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD

goes above the operating voltage lower limit (see Figure 4).

Characteristics of a Sample Subsystem Clock Oscillator Circuit

Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-

designated oscillation characteristics evaluation board and external components with circuit constant values with which

the oscillator vendor confirmed normal and stable oscillation.

Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator

Circuit Constant

Oscillation

Stabilization Time

Nominal

Frequency

Vendor Name

Oscillator

Name

C3

[pF]

C4

[pF]

Rf2

[

Ω]

Rd2

[

Ω]

Operating

Voltage Range

[V]

typ

[s]

max

[s]

Remarks

32.768kHz

The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the

instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the

oscillation to get stabilized after the HOLD mode is reset (see Figure 4).

Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as

possible because they are vulnerable to the influences of the circuit pattern.

Figure 1 CF Oscillator Circuit

Figure 2 XT Oscillator Circuit

Figure 3 AC Timing Measurement Point

0.5VDD

CF2

CF1

C3

Rd2

C4

X’tal

XT2

XT1

Rf2

C1

Rd1

C2

CF

Rf1