Data Transmission

Refer to the application circuit when reading the following description. Data information can be

transmitted onto the positive power line by reducing the voltage level for a short time duration. As the

devices include a voltage regulator which is used as the power supply to the subsystem units, then the

subsystem power supply voltage will not be affected as long as the regulator minimum dropout voltage

is maintained. However a reduction in the power supply will be detected by the C1 internal

comparators. The output of this comparator is connected to an open drain NMOS transistor, Q1, whose

open drain output on pin CX can be connected to a microcontroller input for use as a data signal.

Data Reception

Refer to the application circuit when reading the following description. The individual subsystems can

transmit data to the master controller along the power supply line by using one of its I/O lines to reduce

the positive power line supply line voltage level for a short time duration. An output line on the

subsystem microcontroller should be connected to the TG pin. An internal comparator, C2, whose

positive input is connected to an internal voltage reference, will detect if this pin is pulled low. The

comparator output is connected to an internal open drain NMOS transistor, Q4, which will pull the

CP/TD line low. By connecting a suitable value resistor between the CP/TD pin and the power supply

line, the correct value of power supply voltage reduction can be implemented.

Protection Circuits

The devices include an internal Voltage Detector function which monitors the power supply input

voltage. Should the input power supply voltage fall below a safe level specified by the voltage detector

level, then the voltage detector output will change state and disable the internal regulator thus

removing the power supply source to the subsystem circuits. An internal NMOS transistor whose drain

is connected to the output power supply line, VO will also turn on keeping the VO level close to zero.

This ensures that the subsystem microcontroller receives the proper power on reset conditions. When

power is applied an external capacitor, connected to pin CDLY, together with an internal resistor,

RPU1, implement a power on delay time for the internal LDO.

Rev. 1.00

6

June 30, 2010

HT71D02/HT71D04

Power Line Data Transceiver

P o w e r S u p p l y

V o l t a g e P u l s e

T r a n s m i t t e d b y M a s t e r

C o m p a r a t o r

- v e i n p u t

C o m p a r a t o r

+ v e i n p u t

D a t a P u l s e t o M C U

P u l s e w i d t h d e t e r m i n e d b y e x t e r n a l R C n e t w o r k

V I N

C N

C P / T D

C X

Power Line Data Reception