AD7607 datasheet(8/32 Pages) AD

8 / 32 page

AD7608

Data Sheet

Rev. A | Page 8 of 32

Limit at TMIN, TMAX

Parameter

Min

Typ

Max

Unit

Description

t27

Delay from

RDEE

falling edge to FRSTDATA low

VDRIVE = 3.3 V to 5.25 V

VDRIVE = 2.3 V to 2.7 V

t28

Delay from 16th SCLK falling edge to FRSTDATA low

VDRIVE = 3.3 V to 5.25 V

VDRIVE = 2.3 V to 2.7 V

t29

Delay from

CSEE

rising edge until FRSTDATA three-state enabled

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.

A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.

Timing Diagrams

tCYCLE

tRESET

tCONV

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

RESET

Figure 2.CONVST x Timing—Reading After a Conversion

tCYCLE

tCONV

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

tRESET

RESET

Figure 3. CONVST x Timing—Reading During a Conversion

DATA:

DB[15:0]

FRSTDATA

INVALID

[17:2]

[1:0]

[17:2]

[1:0]

t10

t13

t24

t26

t27

t14

t11

t16

t17

t29

t15

Figure 4. Parallel Mode Separate

CSEE

and

RDEE

Pulses

AD7607 Datenblatt(PDF) 8 Page - Analog Devices

AD7607 Datenblatt(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datenblatt Download

Link URL