SC461 datasheet(19/31 Pages) SEMTECH

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SC461

soft-start sequence. PGOOD is also low after an OVP

event.

Output Under-Voltage Protection

When V

FB falls 25% below its nominal voltage (falls to

450mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tri-

state the MOSFETs. The controller stays off while the

device goes through the automatic fault recovery cycle.

Automatic Fault Recovery

The SC461 includes an automatic recovery feature (hiccup

mode upon fault). If the switcher output is shut down due

to a fault condition, the device uses the SS capacitor as a

timer. Upon fault detection the SS pin is pulled low and

then begins charging through the internal 3μA current

source. When the SS capacitor reaches 67% of VDDA, the

SS pin is again pulled low, after which the SS capacitor

begins another charging cycle. The SS capacitor will be

used for 15 cycles of charging from 0 to 67% of VDDA. (For

Over-voltage and Over-Temperature faults, the count will

be 16 cycles instead of 15). During these cycles the

switcher is off and there is no MOSFET switching.

During the next charging cycle, the normal soft-start

routine is implemented and the MOSFETs begin switch-

ing. Switching continues until the Power Good Start-up

Delay Time is reached. If the switcher output is still in a

fault condition, the switcher will again shut down and

force 15 cycles of SS charging (16 cycles in the case of an

Over-voltage or Over-Temperature fault) before attempt-

ing another soft-start. The long delay between soft-start

cycles reduces the average power loss in the power

components.

The automatic recovery timing is shown in Figure 11.

15 cycles

tHICCUP = 15 x tEN_PGOOD

tEN_PGOOD

67% x VDDA

1 soft-start cycle

fault

applied

15 cycles

1 soft-start cycle

tEN_PGOOD

tHICCUP = 15 x tEN_PGOOD

Figure 11 — Automatic Recovery Timing

The control of the low-side MOSFET during an Over-

voltage fault is handled differently from other faults. If the

fault was due to an over-voltage condition, the DL output

will remain high during 16 SS charging cycles. For all other

faults, the DL output will remain low. However, if the FB

pin exceeds the Over-voltage threshold, the charging of

the SS capacitor will not occur, and the DL output will

remain high. If the FB pin falls below the OVP threshold,

16 SS charging cycles will occur while DL remains high.

When the next start-up cycle commences, DL will drive

low for typically 30us as the controller re-initializes the

internal soft-start routine.

VDDA UVLO and POR

The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib-

its switching and tri-states the DH/DL drivers until VDDA

rises above 2.84V. When VDDA exceeds 2.84V, an internal

POR (Power-On Reset) resets the fault latch and the soft-

start circuitry and then the SC461 is ready to begin a soft-

start cycle. The switcher will shut off if VDDA falls below

2.62V. VDDP does not have UVLO protection.

LDO Regulator

When the LDO is providing bias power to the device, a

minimum 0.1μF capacitor referenced to AGND is required,

along with a minimum 1μF capacitor referenced to PGND

to filter the gate drive pulses. Refer to the PCB Layout

Guidelines section.

ENL Pin and V

IN UVLO

The ENL pin is also used for the V

IN under-voltage lockout

IN UVLO) for the switcher. The VIN UVLO voltage is pro-

grammable via a resistor divider at the V

IN, ENL and AGND

pins. The V

IN UVLO function has a typical threshold of 1.55V

on the V

IN rising edge. The falling edge threshold is 1.24V.

Note that when the V

IN UVLO feature is used, the LDO is

enabled because the ENL pin is above the LDO enable

threshold (0.8V typical). In these cases the SC461 must use

the internal LDO for bias power.

Timing is important when driving ENL with logic and not

using the V

IN UVLO capability. The ENL pin must transition

from high to low within 2 switching cycles to avoid the

PWM output turning off. If ENL goes below the V

IN UVLO

Applications Information (continued)

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