DS28EC20 datasheet(21/27 Pages) MAXIM

21 / 27 page

DS28EC20: 20Kb 1-Wire EEPROM

21 of 27

1-Wire SIGNALING

The DS28EC20 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on

one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the

presence pulse, the bus master initiates all falling edges. The DS28EC20 can communicate at two different

speeds: standard speed and overdrive speed. If not explicitly set into the Overdrive mode, the DS28EC20

communicates at standard speed. While in Overdrive mode the fast timing applies to all waveforms. For operation

at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%.

To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get

from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to

make this rise is seen in Figure 10 as

, and its duration depends on the pullup resistor (R

PUP) used and the

capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS28EC20 when determining a

logical level, not triggering any events.

Figure 10 shows the initialization sequence required to begin any communication with the DS28EC20. A reset

pulse followed by a presence pulse indicates that the DS28EC20 is ready to receive data, given the correct ROM

and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the

line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer exits the Overdrive mode,

returning the device to standard speed. If the DS28EC20 is in Overdrive mode and tRSTL is no longer than 80µs, the

device remains in Overdrive mode. If the device is in Overdrive mode and tRSTL is between 80µs and 480µs, the

device resets, but the communication speed is undetermined.

Figure 10. Initialization Procedure: Reset and Presence Pulse

RESISTOR

MASTER

DS28EC20

tRSTL

tPDL

tRSTH

tPDH

MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”

VPUP

VIHMASTER

VTH

VTL

VILMAX



tREC

tMSP

After the bus master has released the line it goes into Receive mode. Now the 1-Wire bus is pulled to VPUP through

the pullup resistor, or in case of a DS2482-x00 or DS2480B driver, by active circuitry. When the threshold VTH is

crossed, the DS28EC20 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect

a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the

DS28EC20 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum

480µs at standard speed and 48µs at overdrive speed to accommodate other 1-Wire devices.

Read-/Write-Time Slots

Data communication with the DS28EC20 takes place in time slots, which carry a single bit each. Write-time slots

transport data from bus master to slave. Read-time slots transfer data from slave to master. Figure 11 illustrates

the definitions of the write- and read-time slots.

All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the

threshold VTL, the DS28EC20 starts its internal timing generator that determines when the data line is sampled

during a write-time slot and how long data is valid during a read-time slot.

DS28EC20 Datenblatt(PDF) 21 Page - Maxim Integrated Products

DS28EC20 Datenblatt(HTML) 21 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datenblatt Download

Link URL