80C166 datasheet(21/52 Pages) SIEMENS

21 / 52 page

SAB 80C166/83C166

Semiconductor Group

Parallel Ports

The SAB 80C166 provides up to 76 I/O lines which are organized into five input/output ports and

one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)

programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports

which are switched to high impedance state when configured as inputs. During the internal reset, all

port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. Port 0

and Port 1 may be used as address and data lines when accessing external memory, while Port 4

outputs the additional segment address bits A17/A16 in systems where segmentation is enabled to

access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare

outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA, HOLD).

Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR,

BHE, READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels

to the A/D converter. All port lines that are not used for these alternate functions may be used as

general purpose I/O lines.

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral

components is provided by two serial interfaces with identical functionality, Asynchronous/

Synchronous Serial Channels ASC0 and ASC1.

They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family

and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex

synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock.

Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.

For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for

each serial channel.

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit

and terminated by one or two stop bits. For multiprocessor communication, a mechanism to

distinguish address from data bytes has been included (8-bit data + wake up bit mode).

In synchronous mode one data byte is transmitted or received synchronously to a shift clock which

is generated by the SAB 80C166.

A loop back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. A parity bit can automatically be generated on transmission or be

checked on reception. Framing error detection allows to recognize data frames with missing stop

bits. An overrun error will be generated, if the last character received has not been read out of the

receive buffer register at the time the reception of a new character is complete.

80C166 Datenblatt(PDF) 21 Page - Siemens Semiconductor Group