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AD9577 Datenblatt(PDF) 21 Page - Analog Devices

Teilenummer AD9577
Bauteilbeschribung  Clock Generator with Dual PLLs
PDF  44 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9577 Datenblatt(HTML) 21 Page - Analog Devices

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Data Sheet
AD9577
Rev. 0 | Page 21 of 44
OUTPUT JITTER
480
475
470
465
460
455
450
445
440
435
430
86 87 88 89 90 91 92 93 94 95 96 97 98 99
101
100
102
Na
Figure 18. Typical Integrated Random Phase Jitter in fs rms for PLL1 and
OUT0P LVPECL as Feedback Divider Value Na Swept (fXTAL = 25 MHz, V0 = 5,
D0 = 5)
500
440
490
480
470
460
450
Nb
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
Figure 19. Typical Integrated Random Phase Jitter in fs rms for PLL2 and
OUT2P LVPECL as Feedback Divider Value Nb Swept
(fXTAL = 25 MHz, V2 = 5, D2 = 5, Integer-N Mode)



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