LTC3589 datasheet(34/50 Pages) LINER

34 / 50 page

LTC3589/LTC3589-1/

LTC3589-2

3589fe

OPERATION

Figure 16. IRQ and IRQSTAT Status Register Warning Timing

IRQ

IRQSTAT

CLIRQ

3589 F16

TSD OR UV

WARNING

If any enabled regulator output falls more than 7% low

for longer than 25μs PGOOD is pulled LOW and a cor-

responding status bit in the PGSTAT register is set to 0.

The PGOOD pin and PGSTAT status bit remain LOW for

as long as the low voltage condition persists plus 250μs.

An extended low output rail causing the PGOOD pin to

be LOW for longer than 14ms defines a PGOOD timeout

fault condition that triggers a hard reset if not masked in

I2C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD

remains in normal operation.

During a dynamic voltage slew, PGOOD is pulled LOW

unless bit 5 in the dynamic target voltage register for

each regulator is set HIGH. The status register PGSTAT

is unaffected by a dynamic voltage slew.

Undervoltage Detection

The LTC3589 undervoltage (UV) detection circuit will out-

put a fault condition, locking out regulator operation, until

VIN reaches 2.7V. Once VIN is above 2.7V the LTC3589 will

operate normally until VIN drops to 2.55V (typical). When

VIN drops below 2.55V, the fault condition initiates a hard

shutdown reset. Figure 15 shows undervoltage warning

and fault detection levels.

Thermal Shutdown Fault and Warning

Similar to the VIN undervoltage detection circuits the over-

temperature detection circuits check for warning and fault

levels. An overtemperature fault will initiate a fault induced

shutdown. An overtemperature warning sets register bit

IRQSTAT[6] and pulls the IRQ pin LOW.

IRQ Pin and IRQSTAT Status Register Function

The IRQ pin and IRQSTAT status register report PGOOD

timeout fault, VIN undervoltage warning and fault, and

high temperature warning and fault. Table 16 shows the

meaning of the IRQSTAT read-only status register bits.

Table 16. IRQSTAT Read-Only Register Bit Definitions

IRQSTAT[BIT]

VALUE

SETTING

PGOOD Timeout Fault (PGOOD Low >

14ms)

VIN Undervoltage Warning (VIN < 2.9V)

VIN Undervoltage Fault (VIN < 2.6V)

Thermal Limit Warning (TJ > 130°C)

Thermal Limit Fault (TJ > 150°C)

Figure 16 shows the timing of the IRQ and IRQSTAT status

warning) event. When a warning occurs, IRQ is latched

LOW and bit IRQSTAT[4] or IRQSTAT[5] is set. IRQ remains

low and the IRQSTAT status bits remain active until the

I2C CLIRQ command is given and the warning condition

has passed.

Figure 15. UV Detection Hard Reset and Warning Levels

VIN

UNDERVOLTAGE

VIN

FAULT

WARNING

3589 F15

2.55V

2.65V

2.9V

An undervoltage warning sets register bit IRQSTAT[4] and

pulls the IRQ pin LOW.

To minimize standby quiescent current the UVLO and

thermal sensor circuits are disabled when all the regula-

tors are off.

LTC3589 Datenblatt(PDF) 34 Page - Linear Technology

LTC3589 Datenblatt(HTML) 34 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datenblatt Download

Link URL