MPC8569E datasheet(75/127 Pages) FREESCALE

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Ethernet Management Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.7.1.1

MII Management AC Electrical Specifications

The following table provides the MII management AC timing specifications.

The following figure shows the MII management AC timing diagram.

Figure 34. MII Management Interface Timing Diagram

Table 43. MII Management AC Timing Specifications

At recommended operating conditions with LVDD = 3.3 V ± 5%.

Parameter

Symbol1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO valid

tMDKHDV

×(t

plb_clk*8)

—

MDC to MDIO delay

tMDKHDX

(16

× t

plb_clk) – 3

—

(16

× t

plb_clk) + 3

3, 4, 5

MDIO to MDC setup time

tMDDVKH

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDCF

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reaching the valid

state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of

the Mgmt Clock CE_MDC).

3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For

example, with a platform clock of 400 MHz, the min/max delay is 40 ns ± 3 ns.

4. tplb_clk is the QUICC Engine block clock/2.

5. MDC to MDIO Data valid tMDKHDV is a function of clock period and max delay time (tMDKHDX).

(Min setup = cycle time – max delay

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDKHDX

MDIO

(Input)

(Output)

tMDDVKH

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