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SL74HC393D Datenblatt(PDF) 4 Page - System Logic Semiconductor

Teilenummer SL74HC393D
Bauteilbeschribung  Dual 4-Stage Binary Ripple Counter
PDF  7 Pages
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Hersteller  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC393D Datenblatt(HTML) 4 Page - System Logic Semiconductor

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SL74HC393
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
4.5
6.0
5.4
27
32
4.4
22
26
3.6
18
21
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
tPHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Counter)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC
2f+I
CCVCC
40
pF
TIMING REQUIREMENTS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to-55°C
≤85°C
≤125°C
Unit
trec
Minimum Recovery Time, Reset
Inactive to Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Set
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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