SN8P021X/8P011X

SONiX TECHNOLOGY CO., LTD

Page 2

Preliminary

January 2000

4. BLOCK DIAGRAM

5. PIN DESCRIPTION

PIN NAME

TYPE

DESCRIPTION

P1.0 ~ P1.3

I/O

Port 1.0 ~ Port 1.3 bi-direction pins.

RST/VPP

I

System reset inputs pin. Schmitt trigger structure, active “low”, normal stay to “high”.

During program op-code, this pin be pull to 12.5Vdc to reset internal address counter and to

write data into OTP-ROM.

VDD, VSS

P

Power supply input pins.

P2.0 ~ P2.7

I/O

Port 2.0 ~ Port 2.7 bi-direction pins.

XIN

I

Oscillator input pin.

XOUT

O

Oscillator output pin.

P0.0 / INT0

I

Port 0.0 and INT0 trigger pin with schmitt trigger structure.

Note : In order to reduce power consumption, the following procedure must be setup.

a). In the SN8P0211/8P0111 version, P1.2 ~ P1.3 must be programmed to input mode with pull up resistor.

PC

IR

OTP

ROM

H-OSC

TIMING GENERATOR

RAM

SYSTEM REGISTER

ALU

ACC

INTERRUPT

CONTROL

TIMER & COUNTER

PORT 0

PORT 2

PORT 1

FLAGS