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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SN8P1602AX Datenblatt(PDF) 66 Page - SONiX Technology Company |
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SN8P1602AX Datenblatt(HTML) 66 Page - SONiX Technology Company |
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66 / 94 page  SN8P1600 8-bit micro-controller SONiX TECHNOLOGY CO., LTD Page 66 Revision 1.94 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. SN8P1602/1603 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN 0 0 TC0IEN 0 0 0 0 P00IEN Read/Write - - R/W - - - - R/W After reset - - 0 - - - - 0 SN8P1604 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN 0 TC1IEN 0 0 0 0 0 P00IEN Read/Write - R/W - - - - - R/W After reset - 0 - - - - - 0 P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable. TC0IEN : Timer 0 interrupt control bit. 0 = disable, 1 = enable. INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. SN8P1602/1603 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ 0 0 TC0IRQ 0 0 0 0 P00IRQ Read/Write - - R/W - - - - R/W After reset - - 0 - - - - 0 SN8P1604 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ 0 TC1IRQ 0 0 0 0 0 P00IRQ Read/Write - R/W - - - - - R/W After reset - 0 - - - - - 0 P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request. TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request. When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. |
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