SN74HC166AQ1

8BIT PARALLELLOAD SHIFT REGISTER

SCLS538A − AUGUST 2003 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

description/ordering information

This parallel-in or serial-in, serial-out register

features gated clock (CLK, CLK INH) inputs and an

overriding clear (CLR) input. The parallel-in or

serial-in modes are established by the shift / load

(SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial

shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and

synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited.

Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting

one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits

clocking; holding either low enables the other clock input. This allows the system clock to be free running, and

the register can be stopped on command with the other clock input. CLK INH should be changed to the high

level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

SOIC − D

Tape and reel

SN74HC166AIDRQ1

HC166AI

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74HC166AIPWRQ1

HC166AI

† For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SER

A

B

C

D

CLK INH

CLK

GND

SH/LD

H

G

F

E

CLR

D OR PW PACKAGE

(TOP VIEW)

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.