TNETX3100PGC datasheet(73/80 Pages) TI1

73 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Figure 24)

MII receive 100 Mbit/s (xx=ports 00–01)

NO.

MIN

MAX

UNIT

tsu(MXXRXD)1

Setup time, MXXRXD3–MXXRXD0 valid before MXXRCLK

↑

tsu(MXXRXD)2

Setup time, MXXRXD7–MXXRXD0 valid before MXXRCLK

↑

tsu(MXXRXDV)

Setup time, MXXRXDV valid before MXXRCLK

↑

tsu(MXXRXDVX)

Setup time, MXXRXDVX valid before MXXRCLK

↑

tsu(MXXRXER)

Setup time, MXXRXER valid before MXXRCLK

↑

th(MXXRXD)1

Hold time, MXXRXD3–MXXRXD0 valid after MXXRCLK

↑

th(MXXRXD)2

Hold time, MXXRXD7–MXXRXD0 valid after MXXRCLK

↑

th(MXXRXDV)

Hold time, MXXRXDV valid after MXXRCLK

↑

th(MXXRXDVX)

Hold time, MXXRXDVX valid after MXXRCLK

↑

th(MXXRXER)

Hold time, MXXRXER valid after MXXRCLK

↑

MXXRXD3–MXXRXD0 is driven by the PHY on the falling edge of MXXRCLK. MXXRXD3–MXXRXD0 timing

must be met during clock periods when MXXRXDV is asserted. MXXRXDV is asserted and deasserted by the

PHY on the falling edge of MXXRCLK. MXXRXER is driven by the PHY on the falling edge of MXXRCLK

(xx = 00–01).

MXXRCLK

(input)

MXXRXD3–MXXRXD0

MXXRXDV

MXXRXER (inputs)

Figure 24. Ports (00–01) Receive Interface Timing

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