TNETX3110 datasheet(55/65 Pages) TI1

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TNETX3110

ThunderSWITCH

™ 8/3 ETHERNET™ SWITCH

WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS047A – MARCH 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

SDRAM interface

The SDRAM interface observes two types of timing:

D Multicycle timings between commands

D Subcycle timings between signals and DCLK

Figure 15 illustrates the SDRAM interfaces signal timing in which each type of SDRAM command and its

interrelated timings are shown. It is not intended to be representative of any particular receive or transmit buffer

operation.

SDRAM command to command (see Figure 15)

SYMBOL

PARAMETER

MIN

MAX

UNIT

tRSA

MRS to ACTV or REFR

tRC

Row cycle time (ACTV to REFR to next ACTV or REFR)

120

tRAS

Row active time (ACTV to DCAB)

tRP

Row recharge time (DCAB to ACTV, REFR, or MRS)

tRCD

Row to column delay (ACTV to READ or WRT)

tAC3

Column access time [READ (CAS) latency] (READ to data sample)

nCCD

Column address to column address (WRT to next READ or WRT, or READ to next READ)

nCWL

Last data or write to new column address (WRT to next READ or WRT)

tRWD

Read to write delay (READ to next WRT)

tWR

Write recovery time (WRT to DCAB)

DCLK

tRC

tRP

tRWD

tWR

nCWL

nCCD

tRCD

tRAS

tRSA

tAC3

DRAS

DCAS

DD31–DD00

DA13–DA00

SETTINGS

BUFFOP

WRITE

MODE

ROW

WRITE

XXXX

DA10=0

DA10=1

DA10=0

NOOP

ACTV

READ

DCAB

REFR

NOOP

WRT

NOOP

MRS

Figure 15. SDRAM Command to Command

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