SN74HC166AEP

8BIT PARALLELLOAD SHIFT REGISTER

SCLS559 − JANUARY 2004

5

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

MIN

MAX

UNIT

VCC

MIN

MAX

MIN

MAX

UNIT

2 V

6

5

fclock

Clock frequency

4.5 V

31

25

MHz

fclock

Clock frequency

6 V

36

29

MHz

2 V

100

125

CLR low

4.5 V

20

25

tw

Pulse duration

CLR low

6 V

17

21

ns

tw

Pulse duration

2 V

80

100

ns

CLK high or low

4.5 V

16

20

CLK high or low

6 V

14

17

2 V

145

180

SH/LD high before CLK

↑

4.5 V

29

36

SH/LD high before CLK

↑

6 V

25

31

2 V

80

100

SER before CLK

↑

4.5 V

16

20

SER before CLK

↑

6 V

14

17

2 V

100

125

tsu

Setup time

CLK INH low before CLK

↑

4.5 V

20

25

ns

tsu

Setup time

CLK INH low before CLK

↑

6 V

17

21

ns

2 V

80

100

Data before CLK

↑

4.5 V

16

20

Data before CLK

↑

6 V

14

17

2 V

40

50

CLR inactive before CLK

↑

4.5 V

8

10

CLR inactive before CLK

↑

6 V

7

9

2 V

0

0

SH/LD high after CLK

↑

4.5 V

0

0

SH/LD high after CLK

↑

6 V

0

0

2 V

5

5

SER after CLK

↑

4.5 V

5

5

th

Hold time

SER after CLK

6 V

5

5

ns

th

Hold time

2 V

0

0

ns

CLK INH high after CLK

↑

4.5 V

0

0

CLK INH high after CLK

↑

6 V

0

0

2 V

5

5

Data after CLK

↑

4.5 V

5

5

Data after CLK

6 V

5

5