TLC5903

LED DRIVER

SLLS383 – DECEMBER 1999

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

write data to both shift register latches

The shift register latch is selected using the RSEL terminal. The data input method is the same for both shift

register latches. The data is applied to DIN0 to DIN7 input terminal in 8-bits data and transferred synchronizing

to DCLK. The data of DIN0 to DIN7 is transferred by the directions from OUT0 to OUT15 synchronizing to DCLK.

The shift register for brightness control is 1-bit length resulting in one time of DCLK input. The shift register for

the gray scale data is 8-bits length at 8-bit mode resulting in eight times DCLK, and the 16-bit length at 16-bit

mode results in 16 times the DCLK input. At the number of DCLK input for each case, output data appears on

DOUT0 to DOUT7. When LATCH goes from low to high, data is latched internally. Then, when LATCH goes

low, data is held. RSEL switching should be done when DCLK and LATCH are low.

brightness control latch configuration

The brightness control latch is configured as DIN0 corresponds to LSB, and DIN7 to MSB. The lower 5 bits are

assigned for output current adjustment, and the upper 3 bits are for a frequency division ratio setting of GSCLK.

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0

MSB

⋅ ⋅⋅⋅

⋅ ⋅⋅⋅

⋅ ⋅⋅⋅

⋅ ⋅⋅⋅

⋅ ⋅⋅⋅

⋅ ⋅⋅⋅

LSB

0†

0

0

1

1

1

1

1

Frequency division ratio setting of GSCLK

Output current setting

† BC_ENA is low.

output current adjustment – brightness adjustment between ICs

By using the lower 5 bits of the brightness control latch, the output current can be adjusted in 32 steps. When

the output current is set to 100% of the external resistor at 11111h of the latched value, it is adjusted as 1 step

or 32 steps of 1.6% current ratio between 100% and 51.6%. By using this function, the brightness control

between modules (ICs) can be adjusted, sending the desired data externally even if ICs are mounted on a PCB.

When BC_ENA is pulled low, the latch is reset to the initial value of 00011111h, and the output current is set to

100%.

CODE

CURRENT RATIO (%)

20 (mA)

80 (mA)

VIREF (TYP)

MSB 00000 LSB

51.6

10.3

41.3

0.64

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

11110

98.4

19.7

78.7

1.22

11111†

100

20.0

80.0

1.24

† BC_ENA is low.

frequency division ratio setting for GSCLK(clock for gray scale) – panel brightness adjustment

By using the upper 3 bits of the brightness control latch, GSCLK can be divided into a frequency division ratio

of 1/1 to 1/8. If GSCLK is set to 8 times the speed of the frequency (256

× 8 = 2048) during the horizontal scanning

time, the brightness can be adjusted to 8 steps by selecting the frequency division ratio. Thus, the total panel

brightness can be adjusted at once and applied to the brightness of day or night. When BC_ENA is pulled low,

GSCLK is not divided. When BC_ENA is pulled high, the brightness can be adjusted as shown in the following

table.