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CXK581000ATM/AYM/AM/AP

• Write cycle (2) : CE1 control

• Write cycle (3) : CE2 control

∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.

∗2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition.

WR1

is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until

the end of the write cycle.

Data valid

High impedance

Address

OE

CE1

CE2

WE

Data in

Data out

Data valid

High impedance

Address

OE

CE1

CE2

WE

Data in

Data out

(∗3)