| Datenblatt-Suchmaschine für elektronische Bauteile |
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CXP820P60 Datenblatt(PDF) 7 Page - Sony Corporation |
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CXP820P60 Datenblatt(HTML) 7 Page - Sony Corporation |
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7 / 23 page ![]() – 7 – CXP820P60 2 pins Hi-Z Hi-Z Pin After a reset Circuit format PB4/SO0 PB7/SO1 PC0/KR0 to PC7/KR7 8 pins IP Pull-up registor Port C data Port C direction "0" after a reset RD (Port C) Internal data bus ∗1 Large current 12mA ∗2 Pull-up transistor approx. 100k Ω ∗2 "0" after a reset ∗1 Key input signal ∗ Pull-up transistor approx. 100k Ω Pull-up registor Port B data Port B direction "0" after a reset RD (Port B) Internal data bus IP ∗ "0" after a reset Serial data output enable Port B outputput selecton "0" after a reset SO Port C Port B ∗ Pull-up transistor approx. 100k Ω Pull-up registor Port B data Port B direction "0" after a reset RD (Port B) Internal data bus IP ∗ "0" after a reset Schmitt input SCK IN Serial clock output enable Port B output selecton "0" after a reset SCK OUT Port B 2 pins Hi-Z PB2/SCK0 PB5/SCK1 |
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