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LRIS64K Datenblatt(PDF) 30 Page - STMicroelectronics |
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LRIS64K Datenblatt(HTML) 30 Page - STMicroelectronics |
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30 / 100 page ![]() Bit representation and coding LRIS64K 30/100 Doc ID 15336 Rev 11 9.2 Bit coding using two subcarriers 9.3 High data rate A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by 9 pulses at 484.28 kHz (fC/28) as shown in Figure 20. For the Fast commands, the x2 mode is not available. Figure 20. Logic 0, high data rate, two subcarriers A logic 1 starts with 9 pulses at 484.28 kHz (fC/28) followed by 8 pulses at 423.75 kHz (fC/32) as shown in Figure 21. For the Fast commands, the x2 mode is not available. Figure 21. Logic 1, high data rate, two subcarriers 9.4 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz (fC/28) as shown in Figure 22. For the Fast commands, the x2 mode is not available. Figure 22. Logic 0, low data rate, two subcarriers A logic 1 starts with 36 pulses at 484.28 kHz (fC/28) followed by 32 pulses at 423.75 kHz (fC/32) as shown in Figure 23. For the Fast commands, the x2 mode is not available. Figure 23. Logic 1, low data rate, two subcarriers 37.46µs ai12074 37.46µs ai12073 149.84µs ai12072 149.84µs ai12075 |
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