WM8904ECSSLASHR datasheet(129/188 Pages) WOLFSON

129 / 188 page

Pre-Production

WM8904

PP, Rev 3.3, September 2012

129

DEFAULT SEQUENCES

When the WM8904 is powered up, two Control Write Sequences are available through default

settings in both RAM and ROM memory locations. The purpose of these sequences, and the register

write required to initiate them, is summarised in Table 87. In both cases, a single register write will

initiate the sequence.

WSEQ START

INDEX

WSEQ FINISH

INDEX

PURPOSE

TO INITIATE

0 (00h)

22 (16h)

Start-Up sequence

Write 0100h to

25 (19h)

39 (27h)

Shutdown sequence

Write 0119h to

Table 87 Write Sequencer Default Sequences

Note on Shutdown sequence: The instruction at Index Address 25 (19h) shorts the outputs

LINEOUTL and LINEOUTR. If the Line outputs are not in use at the time the sequence is run, then

the sequence could, instead, be started at Index Address 26.

Index addresses 0 to 31 may be programmed to users’ own settings at any time, as described in

“Programming a Sequence”. Users’ own settings remain in memory and are not affected by software

resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is

powered down.

START-UP SEQUENCE

The Start-up sequence is initiated by writing 0100h to Register R111 (6Fh). This single operation

starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in

Table 88.

For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 300ms

to run.

Note that, for fast startup, step 18 may be overwritten with dummy data in order to achieve startup

within 50ms (see “Quick Start-Up and Shutdown”).

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

0 (00h)

R4 (04h)

5 bits

Bit 0

1Ah

ISEL = 10b

BIAS_ENA = 0

(delay = 0.5625ms)

1 (01h)

R5 (05h)

8 bits

Bit 0

47h

VMID_BUF_ENA = 1

VMID_RES[1:0] = 11b

VMID_ENA = 1

(delay = 4.5ms)

2 (02h)

R5 (05h)

2 bits

Bit 1

01h

VMID_RES[1:0] = 01b

(delay = 0.5625ms)

3 (03h)

R4 (04h)

1 bit

Bit 0

01h

BIAS_ENA = 1

(delay = 0.5625ms)

4 (04h)

R14 (0Eh)

2 bits

Bit 0

03h

HPL_PGA_ENA = 1

HPR_PGA_ENA = 1

(delay = 0.5625ms)

5 (05h)

R15 (0Fh)

2 bits

Bit 0

03h

LINEOUTL_PGA_ENA = 1

LINEOUTR_PGA_ENA = 1

(delay = 0.5625ms)

6 (06h)

R22 (16h)

1 bit

Bit 1

01h

CLK_DSP_ENA = 1

(delay = 0.5625ms)

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