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WM8904ECS/R Datenblatt(PDF) 131 Page - Wolfson Microelectronics plc

Teilenummer WM8904ECS/R
Bauteilbeschribung  Ultra Low Power CODEC for Portable Audio Applications
PDF  188 Pages
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Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8904ECS/R Datenblatt(HTML) 131 Page - Wolfson Microelectronics plc

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Pre-Production
WM8904
w
PP, Rev 3.3, September 2012
131
SHUTDOWN SEQUENCE
The Shutdown sequence is initiated by writing 0119h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in
Table 89.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 350ms
to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
25 (19h)
R94 (5Eh)
8 bits
Bit 0
77h
0h
0b
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
(delay = 0.5625ms)
26 (1Ah)
R90 (5Ah)
8 bits
Bit 0
77h
0h
0b
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
(delay = 0.5625ms)
27 (1Bh)
R90 (5Ah)
8 bits
Bit 0
00h
0h
0b
HPL_ENA_OUTP = 0
HPL_ENA_DLY = 0
HPL_ENA = 0
HPR_ENA_OUTP = 0
HPR_ENA_DLY = 0
HPR_ENA = 0
(delay = 0.5625ms)
28 (1Ch)
R94 (5Eh)
8 bits
Bit 0
00h
0h
0b
LINEOUTL_ENA_OUTP = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA = 0
LINEOUTR_ENA_OUTP = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA = 0
(delay = 0.5625ms)
29 (1Dh)
R67 (43h)
4 bits
Bit 0
00h
0h
0b
DCS_ENA_CHAN_0 = 0
DCS_ENA_CHAN_1 = 0
DCS_ENA_CHAN_2 = 0
DCS_ENA_CHAN_3 = 0
(delay = 0.5625ms)
30 (1Eh)
R98 (62h)
1 bit
Bit 0
00h
0h
0b
CP_ENA = 0
(delay = 0.5625ms)
31 (1Fh)
R18 (12h)
2 bits
Bit 2
00h
0h
0b
DACL_ENA = 0
DACR_ENA = 0
(delay = 0.5625ms)
32 (20h)
R22 (16h)
1 bit
Bit 1
00h
0h
0b
CLK_DSP_ENA = 0
(delay = 0.5625ms)
33 (21h)
R14 (0Eh)
2 bits
Bit 0
00h
0h
0b
HPL_PGA_ENA = 0
HPR_PGA_ENA = 0
(delay = 0.5625ms)
34 (22h)
R15 (0Fh)
2 bits
Bit 0
00h
0h
0b
LINEOUTL_PGA_ENA = 0
LINEOUTR_PGA_ENA = 0
(delay = 0.5625ms)
35 (23h)
R4 (04h)
1 bit
Bit 0
00h
0h
0b
BIAS_ENA = 0
(delay = 0.5625ms)
36 (24h)
R5 (05h)
1 bit
Bit 0
00h
Ch
0b
VMID_ENA = 0
(delay = 256.5ms)
37 (25h)
R5 (05h)
1 bit
Bit 0
00h
9h
0b
VMID_ENA = 0
(delay = 32.5ms)
38 (26h)
R5 (05h)
8 bits
Bit 0
00h
0h
0b
VMID_BUF_ENA = 0



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