WM8904ECSSLASHR datasheet(136/188 Pages) WOLFSON

136 / 188 page

WM8904

Pre-Production

PP, Rev 3.3, September 2012

136

Note that, if power is removed from the WM8904 or if a software reset is performed, then the default

sequence will be restored, and the DC offset correction will be necessary on the output paths once

more.

ADDRESS

VALUE

DESCRIPTION

R108 (6Ch)

Write Sequencer 0

0111h

WSEQ_ENA = 1

WSEQ_WRITE_INDEX = 11h

This enables the Write Sequencer and selects WSEQ

Index 17 (11h) for modification

R109 (6Dh)

Write Sequencer 1

00FFh

WSEQ_DATA_WIDTH = 000

WSEQ_DATA_START = 0000

WSEQ_ADDR = FFh

This modifies WSEQ Index 17 (11h) with Dummy step

R110 (6Eh)

Write Sequencer 2

0000h

WSEQ_EOS = 0

WSEQ_DELAY = 0000

WSEQ_DATA = 00h

This modifies WSEQ Index 17 (11h) with Dummy step

R111 (6Fh)

Write Sequencer 3

0100h

WSEQ_ABORT = 0

WSEQ_START = 1

WSEQ_START_INDEX = 00h

This starts the Write Sequencer at Index address 0 (00h)

R33 (21h)

DAC Digital 1

0000h

DAC_MONO = 0

DAC_SB_FILT = 0

DAC_MUTERATE = 0

DAC_UNMUTE_RAMP = 0

DAC_OSR128 = 0

DAC_MUTE = 0

DEEMPH = 00

This un-mutes the DACs

Table 92 Fast Start-up from Standby Control

The WSEQ_BUSY bit (in Register R112, see Table 85) will be set to 1 while the sequence runs.

When this bit returns to 0, the device has been set up and is ready for DAC playback operation.

QUICK SHUTDOWN (DEFAULT SEQUENCE)

The default shutdown sequence assumes the initial device conditions are as configured by the default

start-up sequence. Assuming 12.288MHz input clock, the shutdown sequence will take approximately

350ms to complete.

The following register operation will initiate the default shutdown sequence.

ADDRESS

VALUE

DESCRIPTION

R111 (6Fh)

Write Sequencer 3

0119h

WSEQ_ABORT = 0

WSEQ_START = 1

WSEQ_START_INDEX = 19h

This starts the Write Sequencer at Index address 25 (19h)

Table 93 Quick Shutdown Control

The WSEQ_BUSY bit (in Register R112, see Table 85) will be set to 1 while the sequence runs.

When this bit returns to 0, the system clock can be disabled (CLK_SYS_ENA=0) and MCLK can be

stopped.

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