WM8904ECSSLASHR datasheet(134/188 Pages) WOLFSON

134 / 188 page

WM8904

Pre-Production

PP, Rev 3.3, September 2012

134

The POR

¯¯¯ signal is undefined until AVDD has exceeded the minimum threshold, Vpora Once this

threshold has been exceeded, POR

¯¯¯ is asserted low and the chip is held in reset. In this condition, all

writes to the control interface are ignored. Once AVDD and DCVDD have reached their respective

power on thresholds, POR

¯¯¯ is released high, all registers are in their default state, and writes to the

control interface may take place.

Note that a minimum power-on reset period, TPOR, applies even if AVDD and DCVDD have zero rise

time. (This specification is guaranteed by design rather than test.)

On power down, POR

¯¯¯ is asserted low when any of AVDD or DCVDD falls below their respective

power-down thresholds.

Typical Power-On Reset parameters for the WM8904 are defined in Table 90.

SYMBOL

DESCRIPTION

TYP

UNIT

Vpora

AVDD threshold below which POR is undefined

0.25

Vpora_on

Power-On threshold (AVDD)

1.15

Vpora_off

Power-Off threshold (AVDD)

1.12

Vpord_on

Power-On threshold (DCVDD)

0.57

Vpord_off

Power-Off threshold (DCVDD)

0.55

TPOR

Minimum Power-On Reset period

9.5

s

Table 90 Typical Power-On Reset parameters

Notes:

If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating

level but do not go below Vpora_off or Vpord_off) then the chip does not reset and resumes normal

operation when the voltage is back to the recommended level again.

The chip enters reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This

may be important if the supply is turned on and off frequently by a power management system.

The minimum Tpor period is maintained even if DCVDD and AVDD have zero rise time. This

specification is guaranteed by design rather than test.

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