WM8259

Production Data

w

PD Rev 4.2 April 2007

18

OPERATING MODE TIMING DIAGRAMS

The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video

requirements for operation of the most commonly used modes as shown in Table 3. The diagrams

are identical for both CDS and non-CDS operation.

Note that for extended Mode 4 operation (MCLK:VSMP ratios of 2n:1 where n

≥ 4) the latency is

given by:

Latency (in MCLK periods) = 16.5 + ( n – 4 ) * 2

MCLK

VSMP

VINP

OP[3:0]

(DEL = 00)

OP[3:0]

(DEL = 01)

OP[3:0]

(DEL = 10)

OP[3:0]

(DEL = 11)

16.5 MCLK PERIODS

A B C

D

A B C

D

A B C

D

A B C

D

A B C

D

A B C

A B C

A B C

D

A B C D

A B C

A B C

A B C

A B C D

A B C

D

A B C

D

A B C

D

A B C

D

D

D

D

A B C

D

D

D

D

D

Figure 14 Mode 1 Operation

AB C

AB C

AB C D

AB C

AB C

AB C

AB C

AB C

D

AB C

ABC D

ABC D

AB C

AB

C

C

AB C

AB

C

C

AB C

AB

C

C

AB C

AB

C

C

MCLK

VSMP

(DEL= 00)

VINP

OP[3:0]

(DEL= 01)

OP[3:0]

(DEL = 10)

OP[3:0]

(DEL= 11)

24.5 MCLK PERIODS

OP[3:0]

RESET

SAMPLE

VIDEO

SAMPLE

R

S

V

S

R

S

V

S

R

S

V

S

R

S

V

S

R

S

V

S

R

S

V

S

D

D

D

D

D

D

AB C

AB C

ABC

D

D

D

D

AB C

D

D

ABC

D

D

D

D

D

D

D

D

D

D

D

D

D

Figure 15 Mode 2 Operation