WM8352 datasheet(97/336 Pages) WOLFSON

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Production Data

WM8352

PD, February 2011, Rev 4.4

13.11 COMPANDING

The WM8352 supports A-law and

μ-law companding on both transmit (ADC) and receive (DAC)

sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate

value to the DAC_COMP or ADC_COMP register bits respectively.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R113 (71h)

Companding

Control

ADC_COMPM

ODE

ADC Companding mode select:

0 = μ-law

1 = A-law

(Note: Setting ADC_COMPMODE=1

selects 8-bit mode when DAC_COMP=0

and ADC_COMP=0)

ADC_COMP

ADC Companding enable

0 = disabled

1 = enabled

DAC_COMPM

ODE

DAC Companding mode select:

0 = μ-law

1 = A-law

(Note: Setting DAC_COMPMODE=1

selects 8-bit mode when DAC_COMP=0

and ADC_COMP=0)

DAC_COMP

DAC Companding enable

0 = disabled

1 = enabled

Table 49 Companding Control

Companding involves using a piecewise linear approximation of the following equations (as set out

by ITU-T G.711 standard) for data compression:

μ-law (where μ=255 for the U.S. and Japan):

F(x) = ln( 1 +

μ|x|) / ln( 1 + μ)

-1 ≤ x ≤ 1

law (where A=87.6 for Europe):

F(x) = A|x| / ( 1 + lnA)

} for x ≤ 1/A

F(x) = ( 1 + lnA|x|) / (1 + lnA)

} for 1/A ≤ x ≤ 1

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for

μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs

of data.

Companding converts 13 bits (

μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This

provides greater precision for low amplitude signals than for high amplitude signals, resulting in a

greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word

comprising sign (1 bit), exponent (3 bits) and mantissa (4-bits).

8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows

samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B,

8-bit data words may be transferred consecutively every 8 BCLK cycles.

8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or

ADC_COMPMODE=1 when DAC_COMP=0 and ADC_COMP=0.

BIT7

BIT[6:4]

BIT[3:0]

SIG

EXPONENT

MANTISSA

Table 50 8-bit Companded Word Composition

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