RT7297C datasheet(12/15 Pages) RICHTEK

12 / 15 page

RT7297C

DS7297C-01

September 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

OUT

RMS

OUT(MAX)

OUT

= I

−

CIN and COUT Selection

The input capacitance, CIN, is needed to filter the

trapezoidal current at the source of the high side MOSFET.

To prevent large ripple current, a low ESR input capacitor

sized for the maximum RMS current should be used. The

approximate RMS current is given :

OUT

ESR

8fC

⎡⎤

Δ≤ Δ

⎢⎥

⎣⎦

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT/2. This simple worst case condition is

commonly used for design because even significant

deviations do not offer much relief. Choose a capacitor

rated at a higher temperature than required. Several

capacitors may also be paralleled to meet size or height

requirements in the design. For the input capacitor, two

μF low ESR ceramic capacitors are suggested. For the

suggested capacitor, please refer to Table 3 for more

details. The selection of COUT is determined by the

required ESR to minimize voltage ripple. Moreover, the

amount of bulk capacitance is also a key for COUT selection

to ensure that the control loop is stable. Loop stability

can be checked by viewing the load transient response

as described in a later section.

The output ripple,

ΔVOUT, is determined by :

The output ripple will be the highest at the maximum input

voltage since

ΔIL increases with input voltage. Multiple

capacitors placed in parallel may be needed to meet the

ESR and RMS current handling requirement. Higher values,

lower cost ceramic capacitors are now becoming available

in smaller case sizes. Their high ripple current, high voltage

rating and low ESR make them ideal for switching regulator

applications. However, care must be taken when these

capacitors are used at input and output. When a ceramic

capacitor is used at the input and the power is supplied

by a wall adapter through long wires, a load step at the

output can induce ringing at the input, VIN. At best, this

ringing can couple to the output and be mistaken as loop

instability. At worst, a sudden inrush of current through

the long wires can potentially cause a voltage spike at

VIN large enough to damage the part.

Thermal Considerations

For continuous operation, do not exceed the maximum

operation junction temperature 125

°C. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

Where TJ(MAX) is the maximum operation junction

temperature , TA is the ambient temperature and the

θJAis

the junction to ambient thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance

θJA is layout dependent. For

SOP-8 (Exposed Pad) package, the thermal resistance

θJA is 75°C/W on the standard JEDEC 51-7 four-layers

thermal test board. The maximum power dissipation at

TA = 25

°C can be calculated by following formula :

PD(MAX)

= (125

°C − 25°C) / (75°C/W) = 1.333W

(min.copper area PCB layout)

PD(MAX) = (125

°C − 25°C) / (49°C/W) = 2.04W

(70mm2copper area PCB layout)

The thermal resistance

θJA of SOP-8 (Exposed Pad) is

determined by the package architecture design and the

PCB layout design. However, the package architecture

design had been designed. If possible, it's useful to increase

thermal performance by the PCB layout copper design.

The thermal resistance

θJA can be decreased by adding

copper area under the exposed pad of SOP-8 (Exposed

Pad) package.

As shown in Figure 7, the amount of copper area to which

the SOP-8 (Exposed Pad) is mounted affects thermal

performance. When mounted to the standard

SOP-8 (Exposed Pad) pad (Figure 7.a),

θJA is 75°C/W.

Adding copper area of pad under the SOP-8 (Exposed

Pad) (Figure 7.b) reduces the

θJA to 64°C/W. Even further,

increasing the copper area of pad to 70mm2 (Figure 7.e)

reduces the

θJA to 49°C/W.

RT7297C Datenblatt(PDF) 12 Page - Richtek Technology Corporation

RT7297C Datenblatt(HTML) 12 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Datenblatt Download

Link URL