TTP/C-C2 Communication Controller – Preliminary Data Sheet

AS8202

Rev. 1.0, October 2000

Page 8 of 8

Reset and Oscillator

Pin Name

mode

width

Comment

xin0

in

1

main oscillator input

xout0

out

1

main oscillator output

xin1

in

1

bus guardian oscillator input

xout1

out

1

bus guardian oscillator output

plloff

in

1

PLL disable

resetb

in

1

external reset

Table 1: Reset and Oscillator Ports

External Reset Signal

To issue a reset of the chip the resetb port has to be driven low for at least

power-up the reset must overlap the build-up time of the oscillator circuit.

Integrated Power-On Reset

The Device has an internal Power-On Reset generator. When supply voltage ramps up, the

internal reset signal is kept active (low) for about 33 µs typical.

Parameter

Symbol

Min

Typ

Max

Unit

supply voltage slope

dV/dt

250

-

-

kV/s

power on reset active time after VDD > 1,0V

25

33

49

us

Oscillator circuitry

The internal oscillator cell requires an external quartz or an external oscillator respectively. The

frequency applied on the main clock input (xin0, xout0) can be reduced by a factor of four by

using the internal PLL. In order to generate an internal frequency of 40 MHz using the internal

PLL, an external quartz or quartz oscillator with a frequency of 10 MHz is connected and the

plloff input is tied low. The bus guardian clock has no internal PLL.

Figure 3: Quartz Circuit PLL off

Figure 4: Quartz Circuit PLL on

Figure 5: Oscillator Circuit

xin0

xout1

xin1

10MHz

16MHz

AS8202

‚0‘

xout0

40 MHz

xin0

xout1

xin1

20MHz

16MHz

AS8202

‚1‘

xout0

20 MHz

xin0

xout1

xin1

40MHz

oscillator

16MHz

oscillator

AS8202

‚1‘

xout0

40 MHz

n.c.

n.c.