AD625

REV. D

–13–

–

+

12-BIT

DAS

10k

10k

AD625

10k

10k

–INPUT

–GAIN

SENSE

–GAIN

DRIVE

+GAIN

DRIVE

+GAIN

SENSE

+INPUT

20k

15.6k

3.9k

975k

650k

975k

3.9k

20k

15.6k

Figure 39. SPGA with Multiplexer Error Sources

Figure 39 shows a complete SPGA feeding a 12-bit DAS with a

0 V–10 V input range. This configuration was used in the error

budget analysis shown in Table II. The gain used for the RTI

calculations is set at 16. As the gain is changed, the ON resis-

tance of the multiplexer and the feedback resistance will change,

which will slightly alter the values in the table.

Table II. Errors Induced by Multiplexer to an SPGA

Induced

Specifications

Voltage Offset

Error

AD625C

AD7520KN

Calculation

Induced RTI

RTI Offset

Gain Sense Switch

40 nA

× 170 Ω =

6.8

µV

Voltage

Offset

Resistance

6.8

µV

Current

170

Ω

40 nA

RTI Offset

Gain Sense Differential

60 nA

× 6.8 Ω =

0.41

µV

Voltage

Current

Switch

0.41

µV

60 nA

Resistance

6.8

Ω

RTO Offset Feedback

Differential

2 (0.2 nA

× 20 kΩ) 0.5 µV

Voltage

Resistance

Leakage

= 8

µV/16

20 k

2

+0.2 nA

–0.2 nA

RTO Offset Feedback

Differential

2 (1 nA

× 20 kΩ)

2.5

µV

Voltage

Resistance

Leakage

= 40

µV/16

20 k

Current

2

+1 nA

–1 nA

Total error induced by a typical CMOS multiplexer

to an SPGA at +25

°C

10.21

A

NOTES

20 k

Ω is recommended value (see Resistor Programmable Gain Amplifier section).

will be determined by the difference between the leakages of each “half’’ of the

differential multiplexer. The differential leakage current is multiplied by the

feedback resistance (see Note 1), to determine offset voltage. Because differential

leakage current is not a parameter specified on multiplexer data sheets, the most

extreme difference (one most positive and one most negative) was used for the

calculations in Table II. Typical performance will be much better.

internal capacitance of the multiplexer. Figure 40 shows the settling time vs.

ON resistance at different gain settings for an AD625 based SPGA.

**Switch resistance and leakage current errors can be reduced by using relays.

These capacitances may also be incorporated as part of the

external input protection circuit (see section on Input Protec-

tion). As a general practice every effort should be made to

match the extraneous capacitance at Pins 15 and 2, and Pins 1

and 16, to preserve high ac CMR.

SOFTWARE PROGRAMMABLE GAIN AMPLIFIER

An SPGA provides the ability to externally program precision

gains from digital inputs. Historically, the problem in systems

requiring electronic switching of gains has been the ON resis-

and gain drifts. The AD625 eliminates this problem by making

the gain drive and gain sense pins available (Pins 2, 15, 5, 12;

see Figure 39). Consequently the multiplexer’s ON resistance is

removed from the signal current path. This transforms the ON

resistance error into a small nullable offset error. To clarify this

point, an error budget analysis has been performed in Table II

based on the SPGA configuration shown in Figure 39.

+GAIN

SENSE

+INPUT

–INPUT

RTI NULL

RTI NULL

+GAIN DRIVE

–GAIN DRIVE

NC

REF

A1

A2

AD625

10k

10k

10k

10k

A3

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

–GAIN

SENSE

TTL/DTL TO CMOS LEVEL TRANSLATOR

DECODER/DRIVER

3.9k

975

650

975

3.9k

15.6k

15.6k

20k

20k

AD7502

A0

A1

GND

RTO NULL

RTO NULL

Figure 38. SPGA in a Gain of 16

Figure 38 shows an AD625 based SPGA with possible gains of

the sum of the two 975

Ω resistors and the 650 Ω resistor, or

2600

equals the 15.6 k

Ω resistor plus the 3.9 kΩ resistor, or 19.5 kΩ.

The gain, therefore equals:

+1=

2(19.5 k

Ω)

(2.6 k

Ω)

+1=16

As the switches of the differential multiplexer proceed synchro-

gain settings.