AD6432AST datasheet(15/20 Pages) AD

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AD6432

–15–

REV. 0

Gain Control

The AD6432 contains a Gain TC Compensation circuit that

provides a nominal 80 dB dynamic range of automatic gain

control. The GAIN input pin of the gain circuit is driven by

the AD6421 Automatic Gain Control DAC (AGCDAC), an

integrated auxiliary DAC of the AD6421, controllable by the

radio’s digital processor. This connection should be made

through a single pole RC to reduce high frequency noise into

the gain control circuit. The values shown in Figure 35 provide

a –3 dB point at approximately 1 MHz, sufficient for the gain

control.

Gain control scaling is directly proportional to the reference

voltage applied to Pin GREF and is independent of the power

supply voltage. A nominal 1.2 V reference for GREF can be

provided by the AD6421 through BREFOUT. BREFOUT is

a buffered output version of BREFCAP reference. This refer-

ence output feature is enabled on the AD6421 by setting Bit 2

in control register BCRB (BCRB2). See AD6421 data sheet.

The VGAIN input range for this control signal is 0.2 V– 2.4 V where

gain is maximum at 0.2 V and falls off as VGAIN is increased to

2.4 V. To avoid saturating the input to the baseband converter,

the automatic gain control function of the receiver must limit

the output signal swing of the AD6432 to

±1.2 V, the full signal

range of the input.

Phase-Lock Loop Control

The AD6432 PLL/QVCO circuits require an external frequency

reference for coherent modulation and demodulation of the

baseband and IF signal. The external frequency reference con-

trol for the AD6432 PLL/QVCOs is typically generated through

a 13 MHz voltage controlled temperature compensated crystal

oscillator (VCTCXO). The control voltage for the VCTCXO is

generated by an auxiliary DAC in the AD6421 designated as

the Automatic Frequency Control DAC (AFCDAC). The PLL

loop is closed through the radio’s algorithm signal processor,

which drives the AD6421 AFCDAC.

The AD6432 FREF pin provides the VCTCXO reference sig-

nal to the AD6432 RX quadrature VCO (QVCO) circuit.

The AD6432 FREF input must be an ac coupled signal

200 mV p-p or greater. The reference for the UHF TX QVCO

and RX IF down converter is synthesized from the VCTCXO

output reference signal through an external frequency synthe-

sizer and VCO. This UHF reference is an ac coupled input into

AD6432 LOHI and LOLO pins.

An external series RC network connected between FLTR (Pin

29) and the VPOS supply pin provides the proper loop filter for

the VCO/PLL as shown in Figure 35.

BAND-

PASS

FILTER

FREQUENCY

SYNTHESIZER

VCTCXO

50pF

Ω

100nF

0.1 F

160

Ω

1nF

ITXP

ITXN

QTXP

QTXN

AD6421

IRXP

IRXN

QRXP

QRXN

AFCDAC

MCLK

BREFCAP

BREFOUT

AGCDAC

RAMDAC

POWER CONTROL

50pF

GAIN

GREF

LOLO

LOHI

FREF

QRXN

QRXP

IRXN

IRXP

QTXN

QTXP

ITXN

ITXP

AD6432

Figure 35. AD6432 to AD6421 Interface

Transmit Power Control

A general purpose amplifier is available on the AD6432, which

may be useful as part of an automatic control circuit for the

power amplifier. Open ended, this amplifier will swing full scale

from rail to rail. It is recommended that this amplifier be con-

nected in the unity feedback configuration when not being used

by connecting PCAO to PCAM.

AD6432 EVALUATION BOARD

The AD6432 Evaluation Board is designed to enable measure-

ments of key parameters on the AD6432 IFIC, a device that

provides the complete transmit and receive IF signal processing,

including I/Q modulation and demodulation, necessary to imple-

ment a digital wireless transceiver.

Many of the signal paths into and out of the AD6432 are differ-

ential, which is the preferred interface to and from single supply

CODECS. To facilitate an interface to traditional lab equip-

ment, the following interface circuitry is included on the board.

A 20-pin Berg strip for bias, gain and Inphase and Quadrature

signal interface. End Launch SMA connectors for RF, LO,

MODO and FREF signals and provisions for breaking out

MXOP and IFHI with RF transformers.

A single-ended to differential RF transformer provides a bal-

anced LO drive.

An onboard 1.2 V dc reference IC is provided for application to

GREF.

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