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AD637JD Datenblatt(PDF) 6 Page - Analog Devices

Teilenummer AD637JD
Bauteilbeschribung  High Precision, Wide-Band RMS-to-DC Converter
PDF  10 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD637JD Datenblatt(HTML) 6 Page - Analog Devices

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AD637
REV. E
–6–
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CAV
–VS
+VS
+
ABSOLUTE
VALUE
RMS
OUTPUT
BUFFER
OUTPUT
ANALOG COM
OUTPUT
OFFSET
+
C2
RX
24k
BUFFER INPUT
NC
CHIP
SELECT
DENOMINATOR
INPUT
dB
24k
FOR 1 POLE
FILTER, SHORT
RX AND
REMOVE C3
SIGNAL
INPUT
+
C3
NC
Figure 8. Two Pole Sallen-Key Filter
Figure 9a shows values of CAV and the corresponding averaging
error as a function of sine-wave frequency for the standard rms
connection. The 1% settling time is shown on the right side of
the graph.
Figure 9b shows the relationship between averaging error, signal
frequency settling time and averaging capacitor value. This
graph is drawn for filter capacitor values of 3.3 times the averag-
ing capacitor value. This ratio sets the magnitude of the ac and
dc errors equal at 50 Hz. As an example, by using a 1
µF averag-
ing capacitor and a 3.3
µF filter capacitor, the ripple for a 60 Hz
input signal will be reduced from 5.3% of reading using the
averaging capacitor alone to 0.15% using the single pole filter.
This gives a factor of thirty reduction in ripple and yet the set-
tling time would only increase by a factor of three. The values of
CAV and C2, the filter capacitor, can be calculated for the desired
value of averaging error and settling time by using Figure 9b.
The symmetry of the input signal also has an effect on the mag-
nitude of the averaging error. Table I gives practical component
values for various types of 60 Hz input signals. These capacitor
values can be directly scaled for frequencies other than 60 Hz,
i.e., for 30 Hz double these values, for 120 Hz they are halved.
For applications that are extremely sensitive to ripple, the two pole
configuration is suggested. This configuration will minimize
capacitor values and settling time while maximizing performance.
Figure 9c can be used to determine the required value of CAV,
C2 and C3 for the desired level of ripple and settling time.
INPUT FREQUENCY – Hz
100
0.01
1
100k
10
100
1k
10k
10
1.0
0.1
VALUES FOR CAV AND
1% SETTLING TIME
FOR STATED % OF READING
AVERAGING ERROR*
ACCURACY
2% DUE TO
COMPONENT TOLERANCE
* %dc ERROR + %RIPPLE (Peak)
100
0.01
10
1.0
0.1
Figure 9a.
INPUT FREQUENCY – Hz
100
0.01
1
100k
10
100
1k
10k
10
1.0
0.1
VALUES OF CAV, C2 AND
1% SETTLING TIME FOR
STATED % OF READING
AVERAGING ERROR*
FOR 1 POLE POST FILTER
* %dc ERROR + % PEAK RIPPLE
ACCURACY
20% DUE TO
COMPONENT TOLERANCE
100
0.01
10
1.0
0.1
Figure 9b.
INPUT FREQUENCY – Hz
100
0.01
1
100k
10
100
1k
10k
10
1.0
0.1
VALUES OF CAV, C2 AND C3
AND 1% SETTLING TIME FOR
STATED % OF READING
AVERAGING ERROR*
2 POLL SALLEN-KEY FILTER
* %dc ERROR + % PEAK RIPPLE
ACCURACY
20% DUE TO
COMPONENT TOLERANCE
100
0.01
10
1.0
0.1
Figure 9c.



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